公开(公告)号：US20200066885A1

公开(公告)日：2020-02-27

申请号：US16106344

申请日：2018-08-21

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Vibhor Jain ,  John J. Pekarik ,  Qizhi Liu ,  Pernell Dongmo

IPC: H01L29/732 ,  H01L29/06 ,  H01L29/08

Abstract: Device structures and fabrication methods for a bipolar junction transistor. A trench isolation region surrounds an active region that includes a collector. A base layer is arranged over the active region, and a semiconductor layer is arranged on the base layer. The semiconductor layer includes a stepped profile with a first section having a first width adjacent to the base layer and a second section having a second width that is less than the first width. An emitter is arranged on the second section of the semiconductor layer.

公开(公告)号：US20190326411A1

公开(公告)日：2019-10-24

申请号：US15961364

申请日：2018-04-24

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Vibhor Jain ,  Pernell Dongmo ,  Cameron Luce ,  James W. Adkisson ,  Qizhi Liu

IPC: H01L29/66 ,  H01L29/737 ,  H01L29/06 ,  H01L29/08 ,  H01L29/10

Abstract: Fabrication methods and device structures for a heterojunction bipolar transistor. A trench isolation region is formed that surrounds an active region of semiconductor material, a collector is formed in the active region, and a base layer is deposited that includes a first section over the trench isolation region, a second section over the active region, and a third section over the active region that connects the first section and the second section. An emitter is arranged over the second section of the base layer, and an extrinsic base layer is arranged over the first section of the base layer and the third section of the base layer. The extrinsic base layer includes a first section containing polycrystalline semiconductor material and a second section containing single-crystal semiconductor material. The first and second sections of the extrinsic base layer intersect along an interface that extends over the trench isolation region.

公开(公告)号：US20190229184A1

公开(公告)日：2019-07-25

申请号：US15876530

申请日：2018-01-22

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Steven M. Shank ,  Cameron Luce ,  Pernell Dongmo

IPC: H01L29/06 ,  H01L29/08 ,  H01L21/02 ,  H01L21/764 ,  H01L29/66 ,  H01L21/3065 ,  H01L29/78

Abstract: Structures that integrate airgaps with a field-effect transistor and methods for forming a field-effect transistor with integrated airgaps. A first semiconductor layer is formed on a substrate, and a second semiconductor layer is formed over the first semiconductor layer. A source/drain region of a field-effect transistor is formed in the second semiconductor layer. An airgap is located in the first semiconductor layer, The airgap is arranged in a vertical direction between the source/drain region and the substrate.

公开(公告)号：US20180286968A1

公开(公告)日：2018-10-04

申请号：US15473043

申请日：2017-03-29

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Vibhor Jain ,  Qizhi Liu ,  Alvin J. Joseph ,  Pernell Dongmo

IPC: H01L29/732 ,  H01L29/06 ,  H01L29/08 ,  H01L29/10 ,  H01L29/66 ,  H01L21/311 ,  H01L21/02 ,  H01L29/737 ,  H01L29/165

CPC classification number: H01L29/732 ,  H01L21/02532 ,  H01L21/02636 ,  H01L21/31111 ,  H01L29/0649 ,  H01L29/0804 ,  H01L29/0821 ,  H01L29/1004 ,  H01L29/165 ,  H01L29/66234 ,  H01L29/66242 ,  H01L29/7371

Abstract: Fabrication methods and device structures for bipolar junction transistors and heterojunction bipolar transistors. A first dielectric layer is formed and a second dielectric layer is formed on the first dielectric layer. An opening is etched extending vertically through the first dielectric layer and the second dielectric layer. A collector is formed inside the opening. An intrinsic base, which is also formed inside the opening, has a vertical arrangement relative to the collector.

公开(公告)号：US10720494B2

公开(公告)日：2020-07-21

申请号：US15876530

申请日：2018-01-22

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Steven M. Shank ,  Cameron Luce ,  Pernell Dongmo

IPC: H01L29/06 ,  H01L29/08 ,  H01L29/66 ,  H01L29/78 ,  H01L29/49 ,  H01L21/76 ,  H01L21/02 ,  H01L21/764 ,  H01L21/3065 ,  H01L21/762 ,  H01L21/308 ,  H01L21/768

Abstract: Structures that integrate airgaps with a field-effect transistor and methods for forming a field-effect transistor with integrated airgaps. A first semiconductor layer is formed on a substrate, and a second semiconductor layer is formed over the first semiconductor layer. A source/drain region of a field-effect transistor is formed in the second semiconductor layer. An airgap is located in the first semiconductor layer, The airgap is arranged in a vertical direction between the source/drain region and the substrate.

公开(公告)号：US10134880B2

公开(公告)日：2018-11-20

申请号：US15473043

申请日：2017-03-29

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Vibhor Jain ,  Qizhi Liu ,  Alvin J. Joseph ,  Pernell Dongmo

IPC: H01L21/331 ,  H01L29/732 ,  H01L29/06 ,  H01L29/08 ,  H01L29/10 ,  H01L29/66 ,  H01L21/311 ,  H01L21/02 ,  H01L29/737 ,  H01L29/165

Abstract: Fabrication methods and device structures for bipolar junction transistors and heterojunction bipolar transistors. A first dielectric layer is formed and a second dielectric layer is formed on the first dielectric layer. An opening is etched extending vertically through the first dielectric layer and the second dielectric layer. A collector is formed inside the opening. An intrinsic base, which is also formed inside the opening, has a vertical arrangement relative to the collector.

公开(公告)号：US10818772B2

公开(公告)日：2020-10-27

申请号：US15961364

申请日：2018-04-24

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Vibhor Jain ,  Pernell Dongmo ,  Cameron Luce ,  James W. Adkisson ,  Qizhi Liu

IPC: H01L29/66 ,  H01L29/737 ,  H01L29/10 ,  H01L29/08 ,  H01L29/06

Abstract: Fabrication methods and device structures for a heterojunction bipolar transistor. A trench isolation region is formed that surrounds an active region of semiconductor material, a collector is formed in the active region, and a base layer is deposited that includes a first section over the trench isolation region, a second section over the active region, and a third section over the active region that connects the first section and the second section. An emitter is arranged over the second section of the base layer, and an extrinsic base layer is arranged over the first section of the base layer and the third section of the base layer. The extrinsic base layer includes a first section containing polycrystalline semiconductor material and a second section containing single-crystal semiconductor material. The first and second sections of the extrinsic base layer intersect along an interface that extends over the trench isolation region.

公开(公告)号：US10777668B2

公开(公告)日：2020-09-15

申请号：US16106344

申请日：2018-08-21

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Vibhor Jain ,  John J. Pekarik ,  Qizhi Liu ,  Pernell Dongmo

IPC: H01L29/732 ,  H01L29/08 ,  H01L29/06

Abstract: Device structures and fabrication methods for a bipolar junction transistor. A trench isolation region surrounds an active region that includes a collector. A base layer is arranged over the active region, and a semiconductor layer is arranged on the base layer. The semiconductor layer includes a stepped profile with a first section having a first width adjacent to the base layer and a second section having a second width that is less than the first width. An emitter is arranged on the second section of the semiconductor layer.