公开(公告)号：US20150170735A1

公开(公告)日：2015-06-18

申请号：US14105939

申请日：2013-12-13

Applicant: GLOBALFOUNDRIES INC.

Inventor： Bipul C. PAUL ,  Randy W. MANN ,  Sangmoon J. KIM

IPC: G11C11/412

CPC classification number: G11C11/412 ,  G11C8/16 ,  H01L27/0207 ,  H01L27/1104

Abstract: Dual port static random access memory (SRAM) bitcell structures with improve symmetry in access transistors physical placement are provided. The bitcell structures may include, for example, two pairs of parallel pull-down transistors. The bitcell structures may also include pass-gate transistors PGLA and PGRA forming a first port, and pass-gate transistors PGLB and PGRB forming a second port. The pass-gate transistors PGLA and PGLB may be adjacent one another and a first side of the bitcell structure, and pass-gate transistors PGRA and PGRB may be adjacent one another and a second side of the bitcell structure. Each of the pass-gate transistors PGLA and PGLB may be connected with one of the pull-down transistors of one of the pairs of parallel pull-down transistors. Similarly, each of the pass-gate transistors PGRA and PGRB may be connected with one of the pull-down transistors of the other pair of parallel pull-down transistors.

Abstract translation: 提供了具有提高存取晶体管物理放置对称性的双端口静态随机存取存储器（SRAM）位单元结构。 比特单元结构可以包括例如两对并行下拉晶体管。 比特单元结构还可以包括形成第一端口的通过栅极晶体管PGLA和PGRA，以及形成第二端口的通过栅极晶体管PGLB和PGRB。 通路栅极晶体管PGLA和PGLB可以彼此相邻，并且位单元结构的第一侧，以及栅极晶体管PGRA和PGRB可以彼此相邻，并且位单元结构的第二侧。 每个通栅晶体管PGLA和PGLB可以与一对并联下拉晶体管中的一个的下拉晶体管中的一个连接。 类似地，每个通栅晶体管PGRA和PGRB可以与另一对并联下拉晶体管的下拉晶体管中的一个连接。

公开(公告)号：US20160025805A1

公开(公告)日：2016-01-28

申请号：US14337290

申请日：2014-07-22

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Suresh UPPAL ,  Randy W. MANN ,  William McMahon

IPC: G01R31/28 ,  H01L21/66 ,  H01L23/525

CPC classification number: G01R31/2884 ,  G01R31/2644 ,  H01L22/14 ,  H01L22/34 ,  H01L23/5256 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Wafer test structures and methods of providing wafer test structures are described. The methods include: fabricating multiple test devices and multiple fuse devices on the wafer, each test device having a respective fuse device associated therewith, which open circuits upon failure of the test device; and fabricating a selection circuit operative to selectively connect one test device to a sense contact pad, and the other test devices to a stress contact pad. The selection circuit facilitates sensing one or more electrical signals of the one test device by electrical contact with the sense contact pad, while stress testing the other test devices by electrical contact with the stress contact pad. In one embodiment, each test device has respective first and second switch devices, operative to selectively electrically connect the test device to the sense or stress contact pads. In another embodiment, the method includes wafer testing using the test structure.

Abstract translation: 描述了晶片测试结构和提供晶片测试结构的方法。 这些方法包括：在晶片上制造多个测试装置和多个保险丝装置，每个测试装置具有与其相关联的相应的熔丝装置，其在测试装置故障时断开电路; 以及制造选择电路，其操作以选择性地将一个测试装置连接到感测触点焊盘，并且将其它测试装置连接到应力接触焊盘。 选择电路通过与感测接触焊盘的电接触便于感测一个测试装置的一个或多个电信号，同时通过与应力接触焊盘电接触来测试其它测试装置。 在一个实施例中，每个测试装置具有相应的第一和第二开关装置，其可操作以选择性地将测试装置电连接到感测或应力接触垫。 在另一个实施例中，该方法包括使用测试结构的晶片测试。

公开(公告)号：US20190067262A1

公开(公告)日：2019-02-28

申请号：US15689934

申请日：2017-08-29

Applicant: GLOBALFOUNDRIES INC.

Inventor： Hui ZANG ,  Randy W. MANN

IPC: H01L27/02 ,  H01L27/092 ,  H01L27/11 ,  H01L29/423 ,  H01L23/532 ,  H01L23/522 ,  H01L21/8238 ,  H01L21/768

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to a SRAM structure with alternate gate pitches and methods of manufacture. The structure includes an array of memory cells having a plurality of gate structures with varying gate pitches, the varying gate pitches comprising a first dimension sized for placement of a bitline contact and a second dimension sized for placement of source/drain contacts, the first dimension being larger than the second dimension.