公开(公告)号：US20190148072A1

公开(公告)日：2019-05-16

申请号：US15815308

申请日：2017-11-16

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Robert J. Fox, III ,  Lili Cheng ,  Roderick A. Augur

IPC: H01G4/30 ,  H01G4/005 ,  H01G4/252

Abstract: Methods for fabricating a structure that includes a metal-insulator-metal (MIM) capacitor and structures that include a MIM capacitor. The MIM capacitor includes a layer stack with a first electrode, a second electrode, and a third electrode. The layer stack includes a pilot opening extending at least partially through at least one of the first electrode, the second electrode, and the third electrode. A dielectric layer is arranged over the metal-insulator-metal capacitor, and includes a via opening extending vertically to the pilot opening. A via is arranged in the via opening and the pilot opening. The pilot opening has a cross-sectional area that is less than a cross-sectional area of the via opening.

公开(公告)号：US10236206B2

公开(公告)日：2019-03-19

申请号：US15640748

申请日：2017-07-03

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Robert J. Fox, III

IPC: H01L23/52 ,  H01L21/768 ,  H01L23/532

Abstract: Structures for interconnects and methods for forming interconnects. A dual-damascene opening is formed in a dielectric layer and a first liner is formed on the dielectric layer at one or more sidewalls of the dual-damascene opening. A first conductor layer is formed in a portion of the dual-damascene opening. The first liner is removed from the one or more sidewalls of the dual-damascene opening vertically between the first conductor layer and a top surface of the dielectric layer. After the first liner is removed, a second liner is formed on the dielectric layer at the one or more sidewalls of the dual-damascene opening between the first conductor layer and the top surface of the dielectric layer. A second conductor layer is formed in the dual-damascene opening between the first conductor layer and the top surface of the dielectric layer. The first and second liner materials differ in composition.

公开(公告)号：US20180315707A1

公开(公告)日：2018-11-01

申请号：US15498083

申请日：2017-04-26

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Robert J. Fox, III ,  Kevin M. Boyd ,  Nicholas A. Polomoff ,  Roderick A. Augur ,  Jeannine M. Trewhella

IPC: H01L23/528 ,  H01L23/522 ,  H01L23/00

CPC classification number: H01L23/5283 ,  H01L23/5226 ,  H01L23/562

Abstract: A crack stop structure for an integrated circuit (IC) structure is disclosed. The structure can include: a first crack stop pillar laterally separated from a second crack stop pillar within an insulator region of the IC structure. The first crack stop pillar can include an overlapping via in contact with a top surface and at least one side surface of a first conductive element therebelow. The overlapping via of the first crack stop pillar may be in a given layer of the IC structure, and the second crack stop pillar may include a via in the given layer, the via extending to a different depth than the overlapping via. The via of the second crack stop pillar may be an overlapping via in contact with a top surface and at least one side surface of a second conductive element therebelow.

公开(公告)号：US10580581B2

公开(公告)日：2020-03-03

申请号：US15815308

申请日：2017-11-16

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Robert J. Fox, III ,  Lili Cheng ,  Roderick A. Augur

IPC: H01G4/30 ,  H01G4/252 ,  H01G4/005 ,  H01G4/12 ,  H01L49/02 ,  H01G4/012 ,  H01G4/33 ,  H01G4/232

Abstract: Methods for fabricating a structure that includes a metal-insulator-metal (MIM) capacitor and structures that include a MIM capacitor. The MIM capacitor includes a layer stack with a first electrode, a second electrode, and a third electrode. The layer stack includes a pilot opening extending at least partially through at least one of the first electrode, the second electrode, and the third electrode. A dielectric layer is arranged over the metal-insulator-metal capacitor, and includes a via opening extending vertically to the pilot opening. A via is arranged in the via opening and the pilot opening. The pilot opening has a cross-sectional area that is less than a cross-sectional area of the via opening.

公开(公告)号：US10153232B2

公开(公告)日：2018-12-11

申请号：US15498083

申请日：2017-04-26

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Robert J. Fox, III ,  Kevin M. Boyd ,  Nicholas A. Polomoff ,  Roderick A. Augur ,  Jeannine M. Trewhella

IPC: H01L23/52 ,  H01L23/528 ,  H01L23/522 ,  H01L23/00

Abstract: A crack stop structure for an integrated circuit (IC) structure is disclosed. The structure can include: a first crack stop pillar laterally separated from a second crack stop pillar within an insulator region of the IC structure. The first crack stop pillar can include an overlapping via in contact with a top surface and at least one side surface of a first conductive element therebelow. The overlapping via of the first crack stop pillar may be in a given layer of the IC structure, and the second crack stop pillar may include a via in the given layer, the via extending to a different depth than the overlapping via. The via of the second crack stop pillar may be an overlapping via in contact with a top surface and at least one side surface of a second conductive element therebelow.

公开(公告)号：US10177029B1

公开(公告)日：2019-01-08

申请号：US15790249

申请日：2017-10-23

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Robert J. Fox, III ,  Sunil K. Singh

IPC: H01L21/768 ,  H01L23/522 ,  H01L23/532

Abstract: Interconnect structures and methods for forming an interconnect structure. A sacrificial layer is formed on a substrate and an interconnect opening is formed that extends vertically through the sacrificial layer into the substrate. The interconnect opening is filled with a conductor to form a conductive feature. After filling the interconnect opening with the conductor, a dielectric layer is formed on the sacrificial layer. After the dielectric layer is formed on the sacrificial layer, the sacrificial layer is removed to form an air gap layer arranged vertically between the dielectric layer and the substrate.

公开(公告)号：US20190006234A1

公开(公告)日：2019-01-03

申请号：US15640748

申请日：2017-07-03

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Robert J. Fox, III

IPC: H01L21/768 ,  H01L23/532

Abstract: Structures for interconnects and methods for forming interconnects. A dual-damascene opening is formed in a dielectric layer and a first liner is formed on the dielectric layer at one or more sidewalls of the dual-damascene opening. A first conductor layer is formed in a portion of the dual-damascene opening. The first liner is removed from the one or more sidewalls of the dual-damascene opening vertically between the first conductor layer and a top surface of the dielectric layer. After the first liner is removed, a second liner is formed on the dielectric layer at the one or more sidewalls of the dual-damascene opening between the first conductor layer and the top surface of the dielectric layer. A second conductor layer is formed in the dual-damascene opening between the first conductor layer and the top surface of the dielectric layer. The first and second liner materials differ in composition.