公开(公告)号：US20200035495A1

公开(公告)日：2020-01-30

申请号：US16045111

申请日：2018-07-25

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Dewei Xu ,  Lili Cheng ,  Shinichiro Kakita ,  Ushasree Katakamsetty ,  Roderick A. Augur

IPC: H01L21/304 ,  H01L21/306 ,  H01L21/67 ,  B24B37/005

Abstract: Apparatus and methods of chemical-mechanical polishing of a layer on a wafer. A plurality of polishers arranged on a rotating plate, and a carrier is configured to hold the wafer and to place the layer in contact with the polishers. Each polisher includes a platen and a force-applying device operatively connected to the platen, and the force-applying device is configured to apply a variable force to the platen in order to change a rate of material removal over an area of the layer on the wafer contacted by a polishing pad carried by the platen.

公开(公告)号：US20190148072A1

公开(公告)日：2019-05-16

申请号：US15815308

申请日：2017-11-16

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Robert J. Fox, III ,  Lili Cheng ,  Roderick A. Augur

IPC: H01G4/30 ,  H01G4/005 ,  H01G4/252

Abstract: Methods for fabricating a structure that includes a metal-insulator-metal (MIM) capacitor and structures that include a MIM capacitor. The MIM capacitor includes a layer stack with a first electrode, a second electrode, and a third electrode. The layer stack includes a pilot opening extending at least partially through at least one of the first electrode, the second electrode, and the third electrode. A dielectric layer is arranged over the metal-insulator-metal capacitor, and includes a via opening extending vertically to the pilot opening. A via is arranged in the via opening and the pilot opening. The pilot opening has a cross-sectional area that is less than a cross-sectional area of the via opening.

公开(公告)号：US20180269273A1

公开(公告)日：2018-09-20

申请号：US15463011

申请日：2017-03-20

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Sunil Singh ,  Devender ,  Lili Cheng

IPC: H01L49/02

CPC classification number: H01L28/60

Abstract: Methods for contacting a metal-insulator-metal (MIM) capacitor, as well as structures including a MIM capacitor. A dielectric layer is formed on an electrode of a metal-insulator-metal capacitor. A via is formed that extends vertically through the dielectric layer to the electrode. A conductive plug is formed in the via that contacts the electrode. The dielectric layer is comprised of a polymer, such as polyimide.

公开(公告)号：US20160064472A1

公开(公告)日：2016-03-03

申请号：US14835278

申请日：2015-08-25

Applicant: GLOBALFOUNDRIES, Inc.

Inventor： Lili Cheng ,  Dina H. Triyoso ,  Jeasung Park ,  David Paul Brunco ,  Robert Fox ,  Sanford Chu

IPC: H01L49/02 ,  G06F17/50 ,  H01L21/02 ,  H01L23/522 ,  H01L21/822

CPC classification number: H01L28/60 ,  G06F17/5068 ,  H01L21/02181 ,  H01L21/02189 ,  H01L23/5226 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Integrated circuits including a MIMCAP device and methods of forming the integrated circuits are provided. An exemplary method of forming an integrated circuit including a MIMCAP device includes pre-determining a thickness of at least one of a bottom high-K layer or a top high-K layer of the MIMCAP device, followed by fabricating the MIMCAP device. The pre-determined thickness is established based upon a pre-determined TDDB lifetime for the MIMCAP device and a minimum target capacitance density at an applied voltage bias to be employed for the MIMCAP device. The MIMCAP device includes a bottom electrode and a dielectric layer disposed over the bottom electrode. The dielectric layer includes a stack of individual layers including the bottom high-K layer, the top high-K layer, and a lower-K layer sandwiched therebetween. At least one of the bottom high-K layer or the top high-K layer has the pre-determined thickness.

Abstract translation: 提供了包括MIMCAP器件的集成电路和形成集成电路的方法。 形成包括MIMCAP器件的集成电路的示例性方法包括预先确定MIMCAP器件的底部高K层或顶部高K层中的至少之一的厚度，然后制造MIMCAP器件。 预先确定的厚度是基于MIMCAP器件的预定的TDDB寿命和MIMCAP器件所采用的施加电压偏置下的最小目标电容密度而建立的。 MIMCAP器件包括设置在底部电极上的底部电极和电介质层。 电介质层包括层叠的各层，包括底部高K层，顶部高K层和夹在其间的下部K层。 底部高K层或顶部高K层中的至少一层具有预定厚度。

公开(公告)号：US09583557B2

公开(公告)日：2017-02-28

申请号：US14835278

申请日：2015-08-25

Applicant: GLOBALFOUNDRIES, Inc.

Inventor： Lili Cheng ,  Dina H. Triyoso ,  Jeasung Park ,  David Paul Brunco ,  Robert Fox ,  Sanford Chu

IPC: H01L21/00 ,  H01L49/02 ,  H01L23/522 ,  H01L21/02 ,  G06F17/50

CPC classification number: H01L28/60 ,  G06F17/5068 ,  H01L21/02181 ,  H01L21/02189 ,  H01L23/5226 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Integrated circuits including a MIMCAP device and methods of forming the integrated circuits are provided. An exemplary method of forming an integrated circuit including a MIMCAP device includes pre-determining a thickness of at least one of a bottom high-K layer or a top high-K layer of the MIMCAP device, followed by fabricating the MIMCAP device. The pre-determined thickness is established based upon a pre-determined TDDB lifetime for the MIMCAP device and a minimum target capacitance density at an applied voltage bias to be employed for the MIMCAP device. The MIMCAP device includes a bottom electrode and a dielectric layer disposed over the bottom electrode. The dielectric layer includes a stack of individual layers including the bottom high-K layer, the top high-K layer, and a lower-K layer sandwiched therebetween. At least one of the bottom high-K layer or the top high-K layer has the pre-determined thickness.

Abstract translation: 提供了包括MIMCAP器件的集成电路和形成集成电路的方法。 形成包括MIMCAP器件的集成电路的示例性方法包括预先确定MIMCAP器件的底部高K层或顶部高K层中的至少之一的厚度，然后制造MIMCAP器件。 预先确定的厚度是基于MIMCAP器件的预定的TDDB寿命和MIMCAP器件所采用的施加电压偏置下的最小目标电容密度而建立的。 MIMCAP器件包括设置在底部电极上的底部电极和电介质层。 电介质层包括层叠的各层，包括底部高K层，顶部高K层和夹在其间的下部K层。 底部高K层或顶部高K层中的至少一层具有预定厚度。

公开(公告)号：US10580581B2

公开(公告)日：2020-03-03

申请号：US15815308

申请日：2017-11-16

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Robert J. Fox, III ,  Lili Cheng ,  Roderick A. Augur

IPC: H01G4/30 ,  H01G4/252 ,  H01G4/005 ,  H01G4/12 ,  H01L49/02 ,  H01G4/012 ,  H01G4/33 ,  H01G4/232

Abstract: Methods for fabricating a structure that includes a metal-insulator-metal (MIM) capacitor and structures that include a MIM capacitor. The MIM capacitor includes a layer stack with a first electrode, a second electrode, and a third electrode. The layer stack includes a pilot opening extending at least partially through at least one of the first electrode, the second electrode, and the third electrode. A dielectric layer is arranged over the metal-insulator-metal capacitor, and includes a via opening extending vertically to the pilot opening. A via is arranged in the via opening and the pilot opening. The pilot opening has a cross-sectional area that is less than a cross-sectional area of the via opening.