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公开(公告)号:US20200335552A1
公开(公告)日:2020-10-22
申请号:US16387614
申请日:2019-04-18
Applicant: GLOBALFOUNDRIES Singapore Pte. Ltd.
Inventor: Wei CHANG , Eng Huat TOH , Shyue Seng TAN , Ruchil Kumar JAIN
Abstract: According to various non-limiting embodiments a memory device may include a silicon-on-insulator layer having a conductivity of a first polarity, a first raised structure over the silicon-on-insulator layer, the second raised structure over the silicon-on-insulator layer, an dummy gate arranged between the first raised structure and the second raised structure, and a memory connected to the second raised structure. The first raised structure may have a conductivity of the first polarity, and the second raised structure may include a first diode layer having a conductivity of a second polarity opposite to the first polarity.
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公开(公告)号:US20190259875A1
公开(公告)日:2019-08-22
申请号:US15898669
申请日:2018-02-19
Applicant: GLOBALFOUNDRIES Singapore Pte. Ltd.
Inventor: Liming LI , Shaoqiang ZHANG , Ruchil Kumar JAIN , Raj Verma PURAKH
IPC: H01L29/78 , H01L21/761 , H01L21/8238 , H01L27/06 , H01L29/10 , H01L29/66 , H01L29/08 , H01L29/49
Abstract: A transistor, such as laterally diffused (LD) transistor, having a band region below a drift well is disclosed. The band region and drift well are oppositely doped. The band region is self-aligned to the drift well. The band region reduces the depth of the drift well. A shallower drift well reduces risk of punch-through, improving reliability. In addition, the shallower drift well reduces the drain to body parasitic capacitance which improves performance.
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公开(公告)号:US20190036011A1
公开(公告)日:2019-01-31
申请号:US15661826
申请日:2017-07-27
Applicant: GLOBALFOUNDRIES Singapore Pte. Ltd.
Inventor: Bin LIU , Eng Huat TOH , Ruchil Kumar JAIN
CPC classification number: H01L43/04 , G01R33/0052 , G01R33/0206 , G01R33/077 , H01L27/22 , H01L43/065 , H01L43/14
Abstract: A method of forming a 3D Hall effect sensor and the resulting device are provided. Embodiments include forming a p-type well in a substrate; forming a first n-type well in a first region surrounded by the p-type well in top view; forming a second n-type well in a second region surrounding the p-type well; providing n-type dopant in the first and second n-type wells; and providing p-type dopant in the p-type well and the first n-type well.
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公开(公告)号:US20190259936A1
公开(公告)日:2019-08-22
申请号:US16399393
申请日:2019-04-30
Applicant: GLOBALFOUNDRIES Singapore Pte. Ltd.
Inventor: Bin LIU , Eng Huat TOH , Ruchil Kumar JAIN
Abstract: A method of forming a 3D Hall effect sensor and the resulting device are provided. Embodiments include forming a p-type well in a substrate; forming a first n-type well in a first region surrounded by the p-type well in top view; forming a second n-type well in a second region surrounding the p-type well; providing n-type dopant in the first and second n-type wells; and providing p-type dopant in the p-type well and the first n-type well.
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公开(公告)号:US20180198061A1
公开(公告)日:2018-07-12
申请号:US15402799
申请日:2017-01-10
Applicant: GLOBALFOUNDRIES Singapore Pte. Ltd.
Inventor: Eng Huat TOH , Ruchil Kumar JAIN , Yongshun SUN , Shyue Seng TAN
CPC classification number: H01L43/065 , G01R33/07 , H01L43/04 , H01L43/14
Abstract: A method of forming a 3D Hall effect sensor and the resulting device are provided. Embodiments include forming a p-type well in a substrate; forming a first n-type well in a first region surrounded by the p-type well in top view; forming a second n-type well in a second region surrounding the p-type well; implanting n-type dopant in the first and second n-type wells; and implanting p-type dopant in the p-type well and the first n-type well.
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公开(公告)号:US20190148624A1
公开(公告)日:2019-05-16
申请号:US16243801
申请日:2019-01-09
Applicant: GLOBALFOUNDRIES Singapore Pte. Ltd.
Inventor: Eng Huat TOH , Ruchil Kumar JAIN , Yongshun SUN , Shyue Seng TAN
CPC classification number: H01L43/065 , G01R33/07 , H01L43/04 , H01L43/14
Abstract: A method of forming a 3D Hall effect sensor and the resulting device are provided. Embodiments include forming a p-type well in a substrate; forming a first n-type well in a first region surrounded by the p-type well in top view; forming a second n-type well in a second region surrounding the p-type well; implanting n-type dopant in the first and second n-type wells; and implanting p-type dopant in the p-type well and the first n-type well.
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