公开(公告)号：US11913971B2

公开(公告)日：2024-02-27

申请号：US17183432

申请日：2021-02-24

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Romain H. A. Feuillette ,  David C. Pritchard ,  Elizabeth Strehlow ,  James P. Mazza

IPC: G01P15/00 ,  G01C9/24 ,  G01C9/06 ,  G01C9/20 ,  G01P15/18 ,  G01C9/18

CPC classification number: G01P15/006 ,  G01C9/06 ,  G01C9/20 ,  G01C9/24 ,  G01P15/18 ,  G01C2009/182

Abstract: Disclosed are a motion-sensitive field effect transistor (MSFET), a motion detection system, and a method. The MSFET includes a gate structure with a reservoir containing conductive fluid and gate electrode(s). Given position(s) of the gate electrode(s) and a fill level of the fluid within the reservoir, contact between the gate electrode(s) and the fluid depends upon the orientation the MSFET channel region relative to the top surface of the conductive fluid and the orientation of the MSFET channel region relative to the top surface of the conductive fluid depends upon position in space and/or movement of the MSFET and, particularly, position in space and/or movement of the chip on which the MSFET is formed. An electrical property of the MSFET in response to specific bias conditions varies depending on whether or not or to what extent the gate electrode(s) contact the fluid and is, thus, measurable for sensing chip motion.

公开(公告)号：US20240387668A1

公开(公告)日：2024-11-21

申请号：US18199054

申请日：2023-05-18

Applicant: GlobalFoundries U.S. Inc.

Inventor： Hong Yu ,  David C. Pritchard ,  Navneet K. Jain ,  James P. Mazza ,  Romain H. A. Feuillette

IPC: H01L29/423 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/06 ,  H01L29/417 ,  H01L29/775

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to nanosheet transistor structures with tunable channels and inner sidewall spacers and methods of manufacture. The structure includes: a plurality of stacked semiconductor nanosheets over a semiconductor substrate; a plurality of gate structures surrounding individual nanosheets of the plurality of semiconductor nanosheets, with a lower gate structure comprising a length at least equal to a length of each remaining gate structure of the plurality of gate structures; an inner sidewall spacer adjacent each of the plurality of gate structures; and source/drain regions on opposing sides of the plurality of gate structures, separated therefrom by the inner sidewall spacer.

公开(公告)号：US11722298B2

公开(公告)日：2023-08-08

申请号：US17020895

申请日：2020-09-15

Applicant: GLOBALFOUNDRIES U.S. INC.

Inventor： Romain H. A. Feuillette ,  David C. Pritchard ,  Bernhard J. Wunder ,  Elizabeth Strehlow

IPC: H04L9/08 ,  H04L9/32

CPC classification number: H04L9/0869 ,  H04L9/0825 ,  H04L9/0894 ,  H04L9/3278 ,  H04L9/3297 ,  H04L2209/12

Abstract: Methods and systems generate seeds for public-private key pairs by determining a timestamp value associated with a process design kit (PDK) when a user of the PDK triggers a tool of the PDK while designing an integrated circuit device to have a physical unclonable function device (PUF). The methods and systems generate a first value by mapping the timestamp value to data of the user, generate a second value by mapping the timestamp value to configuration data of the PDK, and generate a third value by mapping the timestamp value to layout data of the PDK. A random number is then generated by applying a function to the first value, the second value, and the third value. A public-private encryption key pair is generated using the random number as a first seed number and using a second number generated by the number generation device as a second seed number.