公开(公告)号：US20210242094A1

公开(公告)日：2021-08-05

申请号：US16776636

申请日：2020-01-30

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Heng Yang ,  David Pritchard ,  Kai Sun ,  Hongru Ren ,  Neha Nayyar ,  Manjunatha Prabhu ,  Elizabeth Strehlow ,  Salvatore Cimino

IPC: H01L21/8238

Abstract: One illustrative vertical transistor device disclosed herein includes a channel region comprising at least one layer of a two-dimensional (2D) material, a bottom source/drain region, a top source/drain region and a gate structure positioned all around at least the at least one layer of a two-dimensional (2D) material.

公开(公告)号：US11722298B2

公开(公告)日：2023-08-08

申请号：US17020895

申请日：2020-09-15

Applicant: GLOBALFOUNDRIES U.S. INC.

Inventor： Romain H. A. Feuillette ,  David C. Pritchard ,  Bernhard J. Wunder ,  Elizabeth Strehlow

IPC: H04L9/08 ,  H04L9/32

CPC classification number: H04L9/0869 ,  H04L9/0825 ,  H04L9/0894 ,  H04L9/3278 ,  H04L9/3297 ,  H04L2209/12

Abstract: Methods and systems generate seeds for public-private key pairs by determining a timestamp value associated with a process design kit (PDK) when a user of the PDK triggers a tool of the PDK while designing an integrated circuit device to have a physical unclonable function device (PUF). The methods and systems generate a first value by mapping the timestamp value to data of the user, generate a second value by mapping the timestamp value to configuration data of the PDK, and generate a third value by mapping the timestamp value to layout data of the PDK. A random number is then generated by applying a function to the first value, the second value, and the third value. A public-private encryption key pair is generated using the random number as a first seed number and using a second number generated by the number generation device as a second seed number.

公开(公告)号：US11094791B1

公开(公告)日：2021-08-17

申请号：US16776711

申请日：2020-01-30

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Heng Yang ,  David Pritchard ,  Kai Sun ,  Hongru Ren ,  Neha Nayyar ,  Manjunatha Prabhu ,  Elizabeth Strehlow ,  Salvatore Cimino

IPC: H01L29/47 ,  H01L29/417 ,  H01L29/16 ,  H01L29/66 ,  H01L29/78 ,  H01L29/08

Abstract: One illustrative device disclosed herein includes a bottom source/drain region and a top source/drain region positioned vertically above at least a portion of the bottom source/drain region, wherein each of the bottom source/drain region and the top source/drain region comprise at least one layer of a two-dimensional (2D) material. The device also includes a substantially vertically oriented semiconductor structure positioned vertically between the bottom source/drain region and the top source/drain region and a gate structure positioned all around an outer perimeter of the substantially vertically oriented semiconductor structure for at least a portion of the vertical height of the substantially vertically oriented semiconductor structure.

公开(公告)号：US11567266B1

公开(公告)日：2023-01-31

申请号：US17551377

申请日：2021-12-15

Applicant: GlobalFoundries U.S. Inc.

Inventor： Judson Holt ,  Yusheng Bian ,  Qizhi Liu ,  Elizabeth Strehlow

IPC: G02B6/34 ,  G02B6/124 ,  G02B6/12 ,  G02B6/293 ,  G02B6/42

Abstract: Structures for a grating coupler and methods of fabricating a structure for a grating coupler. The structure includes a grating coupler having a central portion and edge portions. The central portion and the edge portions define a sidewall, and the central portion and the edge portions have a first longitudinal axis along which the edge portions are arranged in a spaced relationship. Each edge portion projects from the sidewall at an angle relative to the first longitudinal axis. A waveguide core is optically coupled to the grating coupler. The first longitudinal axis is aligned in a first direction, and the waveguide core has a second longitudinal axis that is aligned in a second direction different from the first direction.

公开(公告)号：US20210358865A1

公开(公告)日：2021-11-18

申请号：US16876532

申请日：2020-05-18

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Anton Tokranov ,  Kai Sun ,  Elizabeth Strehlow ,  James Mazza ,  David Pritchard ,  Heng Yang ,  Mohamed Rabie

IPC: H01L23/00 ,  H01L29/06 ,  H01L29/423 ,  H01L29/78 ,  H01L29/66

Abstract: An illustrative device disclosed herein includes a semiconductor substrate and a FinFET transistor device positioned above the semiconductor substrate, wherein the FinFET transistor device has a single active fin structure. The device also includes an electrically inactive dummy fin structure positioned adjacent the single active fin structure, wherein the electrically inactive dummy fin structure is electrically inactive with respect to electrical operation of the FinFET transistor having the single active fin.

公开(公告)号：US20210242316A1

公开(公告)日：2021-08-05

申请号：US16776711

申请日：2020-01-30

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Heng Yang ,  David Pritchard ,  Kai Sun ,  Hongru Ren ,  Neha Nayyar ,  Manjunatha Prabhu ,  Elizabeth Strehlow ,  Salvatore Cimino

IPC: H01L29/417 ,  H01L29/16 ,  H01L29/08 ,  H01L29/78 ,  H01L29/66

Abstract: One illustrative device disclosed herein includes a bottom source/drain region and a top source/drain region positioned vertically above at least a portion of the bottom source/drain region, wherein each of the bottom source/drain region and the top source/drain region comprise at least one layer of a two-dimensional (2D) material. The device also includes a substantially vertically oriented semiconductor structure positioned vertically between the bottom source/drain region and the top source/drain region and a gate structure positioned all around an outer perimeter of the substantially vertically oriented semiconductor structure for at least a portion of the vertical height of the substantially vertically oriented semiconductor structure.

公开(公告)号：US20240162090A1

公开(公告)日：2024-05-16

申请号：US17985487

申请日：2022-11-11

Applicant: GlobalFoundries U.S. Inc.

Inventor： James Mazza ,  David Pritchard ,  Romain Feuillette ,  Elizabeth Strehlow ,  Hongru Ren

IPC: H01L21/768 ,  H01L21/8238 ,  H01L23/522 ,  H01L23/528 ,  H01L27/092

CPC classification number: H01L21/76897 ,  H01L21/823871 ,  H01L23/5226 ,  H01L23/528 ,  H01L27/092

Abstract: Structures with features formed by self-aligned double patterning and methods of self-aligned multiple patterning. The structure comprises a first field-effect transistor including a first gate and a first protrusion projecting laterally from the first gate, and a second field-effect transistor including a second gate and a second protrusion projecting laterally from the second gate. The second gate and the second protrusion are spaced in a lateral direction from the first gate and the first protrusion. The structure further comprises a gate contact connecting the first protrusion of the first gate to the second protrusion the second gate.

公开(公告)号：US20230132912A1

公开(公告)日：2023-05-04

申请号：US17515914

申请日：2021-11-01

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： James P. Mazza ,  Elizabeth Strehlow ,  Motoi Ichihashi ,  Xuelian Zhu ,  Jia Zeng

IPC: H01L29/423 ,  H01L23/528

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to a logic cell layout design for high density transistors and methods of manufacture. The structure includes a plurality of active gates in a high density transistor, and at least one dummy gate which is continuous and is adjacent to at least one active gate of the active gates in a multi-row cell of the high density transistor.

公开(公告)号：US11276651B2

公开(公告)日：2022-03-15

申请号：US16876532

申请日：2020-05-18

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Anton Tokranov ,  Kai Sun ,  Elizabeth Strehlow ,  James Mazza ,  David Pritchard ,  Heng Yang ,  Mohamed Rabie

IPC: H01L23/00 ,  H01L29/06 ,  H01L29/66 ,  H01L29/423 ,  H01L29/78

Abstract: An illustrative device disclosed herein includes a semiconductor substrate and a FinFET transistor device positioned above the semiconductor substrate, wherein the FinFET transistor device has a single active fin structure. The device also includes an electrically inactive dummy fin structure positioned adjacent the single active fin structure, wherein the electrically inactive dummy fin structure is electrically inactive with respect to electrical operation of the FinFET transistor having the single active fin.

公开(公告)号：US12046651B2

公开(公告)日：2024-07-23

申请号：US17515914

申请日：2021-11-01

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： James P. Mazza ,  Elizabeth Strehlow ,  Motoi Ichihashi ,  Xuelian Zhu ,  Jia Zeng

IPC: H01L27/02 ,  H01L23/528 ,  H01L29/423

CPC classification number: H01L29/42376 ,  H01L23/5286

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to a logic cell layout design for high density transistors and methods of manufacture. The structure includes a plurality of active gates in a high density transistor, and at least one dummy gate which is continuous and is adjacent to at least one active gate of the active gates in a multi-row cell of the high density transistor.