公开(公告)号：US11694757B2

公开(公告)日：2023-07-04

申请号：US17860380

申请日：2022-07-08

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Balaji Jayaraman ,  Toshiaki Kirihata ,  Amit K. Mishra

IPC: G11C17/18 ,  G11C29/50

CPC classification number: G11C17/18 ,  G11C29/50004

Abstract: The present disclosure relates to integrated circuits, and more particularly, to a method for identifying unprogrammed bits for one-time-programmable memory (OTPM) and a corresponding structure. In particular, the present disclosure relates to a structure including: a read circuit configured to perform at least one read operation at an address for a twin-cell one-time-programmable-memory (OTPM); and a comparison circuit configured to identify whether at least one bit of the address for the twin-cell OTPM has been programmed based on the at least one read operation.

公开(公告)号：US11380373B1

公开(公告)日：2022-07-05

申请号：US17317938

申请日：2021-05-12

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Mohamed A. Nour ,  Peter C. Paliwoda ,  Byoung-Woon B Min ,  Toshiaki Kirihata

IPC: G11C7/00 ,  G11C7/06 ,  G11C7/10 ,  G11C8/10 ,  G11C16/04 ,  G11C11/22

Abstract: Disclosed is a memory structure including an array of memory cells and a read circuit. The read circuit includes two registers configured to capture and store two different digital-to-analog converter (DAC) codes, which correspond to two different reference currents that approximate two different output currents generated on a bitline during consecutive single-ended current sensing processes directed to the same selected memory cell but using different input voltages. Optionally, the read circuit can also include a current-voltage (I-V) slope calculator, which uses the two different DAC codes to calculate an I-V slope characteristic of the selected memory cell, and a bit generator, which performs a comparison of the I-V slope characteristic and a reference I-V slope characteristic and based on results of the comparison, generates and outputs a bit with a logic value that represents the data storage state of the selected memory cell. Also disclosed is an associated method.

公开(公告)号：US11417407B1

公开(公告)日：2022-08-16

申请号：US17220321

申请日：2021-04-01

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Balaji Jayaraman ,  Toshiaki Kirihata ,  Amit K. Mishra

IPC: G11C17/18 ,  G11C29/50

Abstract: The present disclosure relates to integrated circuits, and more particularly, to a method for identifying unprogrammed bits for one-time-programmable memory (OTPM) and a corresponding structure. In particular, the present disclosure relates to a structure including: a read circuit configured to perform at least one read operation at an address for a twin-cell one-time-programmable-memory (OTPM); and a comparison circuit configured to identify whether at least one bit of the address for the twin-cell OTPM has been programmed based on the at least one read operation.

公开(公告)号：US11329836B1

公开(公告)日：2022-05-10

申请号：US17199515

申请日：2021-03-12

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Toshiaki Kirihata ,  Balaji Jayaraman ,  Chandrahasa Reddy Dinnipati ,  Ramesh Raghavan

IPC: H04L9/32 ,  G11C7/06 ,  G11C8/10

Abstract: A Physically Unclonable Function (PUF) structure includes an array of twin cells divided into two portions: one with first columns and one with second columns. Cells in each first column are connected to a corresponding pair of first bitlines. Cells in each second column are connected to a corresponding pair of second bitlines. A first column decoder is connected to the first bitlines and to a first input of sense amplifier (SA) and a second column decoder is connected to the second bitlines and to a second input of SA. Each read operation to generate a bit is directed to a first cell in a first column and a second cell in a second column and, during the read operation, signals on only one first bitline of the first column containing the first cell and only one second bitline of the second column containing the second cell are compared.

公开(公告)号：US11056208B1

公开(公告)日：2021-07-06

申请号：US16801728

申请日：2020-02-26

Applicant: GLOBALFOUNDRIES U.S. INC.

Inventor： Balaji Jayaraman ,  Ramesh Raghavan ,  Rajesh Reddy Tummuru ,  Toshiaki Kirihata

IPC: G11C17/00 ,  G11C17/18 ,  G11C17/16

Abstract: The present disclosure relates to a data dependent sense amplifier with symmetric margining. In particular, the present disclosure relates to a structure including a bias generator circuit that is configured to provide symmetric margining between two logic states of a memory circuit.

公开(公告)号：US11367734B2

公开(公告)日：2022-06-21

申请号：US16781527

申请日：2020-02-04

Applicant: GLOBALFOUNDRIES U.S. INC.

Inventor： Faraz Khan ,  Dan Moy ,  Norman W. Robson ,  Robert Katz ,  Darren L. Anand ,  Toshiaki Kirihata

IPC: H01L29/792 ,  H01L27/11568 ,  G11C16/08 ,  G11C16/24 ,  H01L27/11573

Abstract: The present disclosure generally relates to semiconductor structures and, more particularly, to charge trap memory devices and methods of manufacture and operation. The semiconductor memory includes: a charge trap transistor comprising a gate structure, a source region and a drain region; and a self-heating circuit which selectively applies an alternating bias direction between the source region and the drain region of the charge trap transistor to provide an erase operation or a programming operation of the charge trap transistor.