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    MEMORY ASSEMBLY WITH BODY BIASING AND RELATED METHODS
    3.
    发明公开
    MEMORY ASSEMBLY WITH BODY BIASING AND RELATED METHODS 审中-公开

    公开(公告)号：US20240304258A1

    公开(公告)日：2024-09-12

    申请号：US18178926

    申请日：2023-03-06

    Applicant: GlobalFoundries U.S. Inc.

    Inventor： Ramesh Raghavan ,  Chandrahasa Reddy Dinnipati ,  Philipp Bernhard Mosch

    IPC: G11C16/26 ,  G11C16/34

    CPC classification number: G11C16/26 ,  G11C16/34

    Abstract: Embodiments of the disclosure provide a memory assembly with body biasing and related methods to operate such a structure. A structure according to the disclosure includes a memory cell having a pair of memory transistors each having a gate coupled to a word line. A pair of diode-connected transistors each have a source/drain (S/D) terminal coupled to a respective S/D terminal of one of the pair of memory transistors through a multiplexer. A bias voltage source is coupled to each body of the pair of diode-connected transistors or each body of the pair of memory transistors. The bias voltage source applies a different bias voltage to each body of the pair of diode-connected transistors or each body of the pair of memory transistors.

    Twin cell memory-based physically unclonable function
    5.
    发明授权
    Twin cell memory-based physically unclonable function 有权

    公开(公告)号：US11329836B1

    公开(公告)日：2022-05-10

    申请号：US17199515

    申请日：2021-03-12

    Applicant: GLOBALFOUNDRIES U.S. Inc.

    Inventor： Toshiaki Kirihata ,  Balaji Jayaraman ,  Chandrahasa Reddy Dinnipati ,  Ramesh Raghavan

    IPC: H04L9/32 ,  G11C7/06 ,  G11C8/10

    Abstract: A Physically Unclonable Function (PUF) structure includes an array of twin cells divided into two portions: one with first columns and one with second columns. Cells in each first column are connected to a corresponding pair of first bitlines. Cells in each second column are connected to a corresponding pair of second bitlines. A first column decoder is connected to the first bitlines and to a first input of sense amplifier (SA) and a second column decoder is connected to the second bitlines and to a second input of SA. Each read operation to generate a bit is directed to a first cell in a first column and a second cell in a second column and, during the read operation, signals on only one first bitline of the first column containing the first cell and only one second bitline of the second column containing the second cell are compared.

    Sense circuit and high-speed memory structure incorporating the sense circuit
    6.
    发明授权
    Sense circuit and high-speed memory structure incorporating the sense circuit 有权

    公开(公告)号：US12051465B2

    公开(公告)日：2024-07-30

    申请号：US17812485

    申请日：2022-07-14

    Applicant: GlobalFoundries U.S. Inc.

    Inventor： Chandrahasa Reddy Dinnipati ,  Bipul C. Paul ,  Ramesh Raghavan

    IPC: G11C13/00 ,  G11C11/16

    CPC classification number: G11C13/004 ,  G11C11/1673 ,  G11C2013/0054 ,  G11C2213/79

    Abstract: Disclosed is a sense circuit with first and second branches connected to first and second inputs of an amplifier. The first branch includes series-connected first transistors between a voltage rail and a data line and a first node between two first transistors and connected to the first input. First transistors on either side of the first node receive corresponding gate bias voltages. The second branch includes series-connected second transistors between the voltage rail and a reference device and a second node between two second transistors and connected to the second input. One first transistor and one second transistor share a common control signal. The first and second branches independently and concurrently generate data and reference voltages on the first and second nodes and the difference between them is sensed by the amplifier. Also disclosed are a non-volatile memory structure incorporating the sense circuit and a method.

    NON-VOLATILE MEMORY STRUCTURE WITH SINGLE CELL OR TWIN CELL SENSING
    7.
    发明公开
    NON-VOLATILE MEMORY STRUCTURE WITH SINGLE CELL OR TWIN CELL SENSING 审中-公开

    公开(公告)号：US20240177770A1

    公开(公告)日：2024-05-30

    申请号：US18058992

    申请日：2022-11-28

    Applicant: GlobalFoundries U.S. Inc.

    Inventor： Bipul C. Paul ,  Chandrahasa Reddy Dinnipati

    IPC: G11C13/00

    CPC classification number: G11C13/004 ,  G11C13/0004 ,  G11C13/0026 ,  G11C2013/0042 ,  G11C2213/70

    Abstract: A non-volatile memory (NVM) structure includes an array of memory cells. Within the array, data is stored in single cells or twin cells. The structure also includes switch circuits and sense amplifiers. Each switch circuit is connected between bitlines for a group of columns and a corresponding sense amplifier and establishes electrical connections to enable either single cell sensing or twin cell sensing. In single cell sensing, a data signal on a bitline connected to a memory cell is compared to a reference signal. In twin cell sensing, true and complement data signals on two bitlines connected to two memory cells are compared to each other. Since twin cell sensing compares true and complement data signals and does not require a reference signal, twin cell sensing is relatively accurate without the need for trim bits. Thus, the structure can store trim cells, accurately sense them, and subsequently use them.

    SENSE CIRCUIT AND HIGH-SPEED MEMORY STRUCTURE INCORPORATING THE SENSE CIRCIUT
    9.
    发明公开
    SENSE CIRCUIT AND HIGH-SPEED MEMORY STRUCTURE INCORPORATING THE SENSE CIRCIUT 审中-公开

    公开(公告)号：US20240021243A1

    公开(公告)日：2024-01-18

    申请号：US17812485

    申请日：2022-07-14

    Applicant: GlobalFoundries U.S. Inc.

    Inventor： Chandrahasa Reddy Dinnipati ,  Bipul C. Paul ,  Ramesh Raghavan

    IPC: G11C13/00 ,  G11C11/16

    CPC classification number: G11C13/004 ,  G11C11/1673 ,  G11C2213/79 ,  G11C2013/0054

    Abstract: Disclosed is a sense circuit with first and second branches connected to first and second inputs of an amplifier. The first branch includes series-connected first transistors between a voltage rail and a data line and a first node between two first transistors and connected to the first input. First transistors on either side of the first node receive corresponding gate bias voltages. The second branch includes series-connected second transistors between the voltage rail and a reference device and a second node between two second transistors and connected to the second input. One first transistor and one second transistor share a common control signal. The first and second branches independently and concurrently generate data and reference voltages on the first and second nodes and the difference between them is sensed by the amplifier. Also disclosed are a non-volatile memory structure incorporating the sense circuit and a method.

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