公开(公告)号：US11881258B2

公开(公告)日：2024-01-23

申请号：US17377769

申请日：2021-07-16

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Ramesh Raghavan ,  Balaji Jayaraman ,  Chandrahasa Reddy Dinnipati

IPC: G11C11/419 ,  H04L9/32 ,  H03K19/21 ,  G11C11/418

CPC classification number: G11C11/419 ,  H03K19/21 ,  H04L9/3278 ,  G11C11/418

Abstract: Embodiments of the present disclosure provide an apparatus including: a sense amplifier coupled to a memory array and having a set of output terminals, a latch coupled to a first output terminal of the sense amplifier, and a comparator coupled to the latch and a second output terminal of the sense amplifier.

公开(公告)号：US11694757B2

公开(公告)日：2023-07-04

申请号：US17860380

申请日：2022-07-08

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Balaji Jayaraman ,  Toshiaki Kirihata ,  Amit K. Mishra

IPC: G11C17/18 ,  G11C29/50

CPC classification number: G11C17/18 ,  G11C29/50004

Abstract: The present disclosure relates to integrated circuits, and more particularly, to a method for identifying unprogrammed bits for one-time-programmable memory (OTPM) and a corresponding structure. In particular, the present disclosure relates to a structure including: a read circuit configured to perform at least one read operation at an address for a twin-cell one-time-programmable-memory (OTPM); and a comparison circuit configured to identify whether at least one bit of the address for the twin-cell OTPM has been programmed based on the at least one read operation.

公开(公告)号：US12176053B2

公开(公告)日：2024-12-24

申请号：US17380688

申请日：2021-07-20

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Ramesh Raghavan ,  Balaji Jayaraman ,  Ming Yin

IPC: G11C29/00 ,  G11C7/12 ,  G11C8/08 ,  G11C29/50

Abstract: The present disclosure relates to integrated circuits, and more particularly, to a wordline system architecture supporting an erase operation and current-voltage (I-V) characterization and methods of manufacture and operation. In particular, the present disclosure relates to a structure including: a twin cell circuit which is connected to a wordline of a memory array; a sourceline driver which is connected to a sourceline of the memory array for providing a cell level current-voltage (I-V) access of the twin cell circuit; and an integrated analog multiplexor which is connected to the twin cell circuit.

公开(公告)号：US20230012844A1

公开(公告)日：2023-01-19

申请号：US17377769

申请日：2021-07-16

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Ramesh Raghavan ,  Balaji Jayaraman ,  Chandrahasa Reddy Dinnipati

IPC: G11C11/419 ,  H03K19/21 ,  H04L9/32

Abstract: Embodiments of the present disclosure provide an apparatus including: a sense amplifier coupled to a memory array and having a set of output terminals, a latch coupled to a first output terminal of the sense amplifier, and a comparator coupled to the latch and a second output terminal of the sense amplifier.

公开(公告)号：US11417407B1

公开(公告)日：2022-08-16

申请号：US17220321

申请日：2021-04-01

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Balaji Jayaraman ,  Toshiaki Kirihata ,  Amit K. Mishra

IPC: G11C17/18 ,  G11C29/50

Abstract: The present disclosure relates to integrated circuits, and more particularly, to a method for identifying unprogrammed bits for one-time-programmable memory (OTPM) and a corresponding structure. In particular, the present disclosure relates to a structure including: a read circuit configured to perform at least one read operation at an address for a twin-cell one-time-programmable-memory (OTPM); and a comparison circuit configured to identify whether at least one bit of the address for the twin-cell OTPM has been programmed based on the at least one read operation.

公开(公告)号：US11329836B1

公开(公告)日：2022-05-10

申请号：US17199515

申请日：2021-03-12

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Toshiaki Kirihata ,  Balaji Jayaraman ,  Chandrahasa Reddy Dinnipati ,  Ramesh Raghavan

IPC: H04L9/32 ,  G11C7/06 ,  G11C8/10

Abstract: A Physically Unclonable Function (PUF) structure includes an array of twin cells divided into two portions: one with first columns and one with second columns. Cells in each first column are connected to a corresponding pair of first bitlines. Cells in each second column are connected to a corresponding pair of second bitlines. A first column decoder is connected to the first bitlines and to a first input of sense amplifier (SA) and a second column decoder is connected to the second bitlines and to a second input of SA. Each read operation to generate a bit is directed to a first cell in a first column and a second cell in a second column and, during the read operation, signals on only one first bitline of the first column containing the first cell and only one second bitline of the second column containing the second cell are compared.

公开(公告)号：US11056208B1

公开(公告)日：2021-07-06

申请号：US16801728

申请日：2020-02-26

Applicant: GLOBALFOUNDRIES U.S. INC.

Inventor： Balaji Jayaraman ,  Ramesh Raghavan ,  Rajesh Reddy Tummuru ,  Toshiaki Kirihata

IPC: G11C17/00 ,  G11C17/18 ,  G11C17/16

Abstract: The present disclosure relates to a data dependent sense amplifier with symmetric margining. In particular, the present disclosure relates to a structure including a bias generator circuit that is configured to provide symmetric margining between two logic states of a memory circuit.