公开(公告)号：US20230197707A1

公开(公告)日：2023-06-22

申请号：US17554222

申请日：2021-12-17

Applicant: GlobalFoundries U.S. Inc.

Inventor： Meng Miao ,  Alain Loiseau ,  Souvick Mitra ,  Wei Liang ,  Robert J. Gauthier, JR. ,  Anindya Nath

IPC: H01L27/02 ,  H01L27/12 ,  H01L29/74

CPC classification number: H01L27/0248 ,  H01L27/1207 ,  H01L29/7436

Abstract: Disclosed are embodiments of a semiconductor structure that includes a semiconductor-controlled rectifier (e.g., for electrostatic discharge (ESD) protection). The SCR can be readily integrated into advanced semiconductor-on-insulator processing technology platforms (e.g., a fully depleted silicon-on-insulator (FDSOI) processing technology platform) that employ hybrid semiconductor substrates (i.e., semiconductor substrates with both bulk semiconductor and semiconductor-on-insulator regions) and is configured with an on-Pwell semiconductor-on-insulator gate structure that is tied to an anode terminal to effectively lower the SCR trigger voltage. To further lower the trigger voltage of the SCR, the Pwell on which the gate structure sits may be made narrower than the gate structure and/or the doping profile of the Pwell on which the gate structure sits may be graded (e.g., P to P- closer to insulator layer). Additionally, to minimize parasitic capacitance, the gate structure may be shorter in length than contact regions parallel and adjacent thereto.

公开(公告)号：US11658480B2

公开(公告)日：2023-05-23

申请号：US17068967

申请日：2020-10-13

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Anindya Nath ,  Zhiqing Li ,  Souvick Mitra ,  Alain Loiseau ,  Wei Liang

IPC: H02H9/04 ,  H01L27/02

CPC classification number: H02H9/046 ,  H01L27/0248 ,  H01L27/0262 ,  H01L27/0266

Abstract: Embodiments of the disclosure provide an electrostatic discharge (ESD) device, including: an input pad; an underlapped field effect transistor (UL-FET) with a trigger voltage Vt, including: an underlapped drain region coupled to the input pad; a source region coupled to ground; and a gate structure coupled to the input pad; and a blocking layer separating the underlapped drain region from the gate structure of the UL-FET by an underlap distance.

公开(公告)号：US20220115864A1

公开(公告)日：2022-04-14

申请号：US17068967

申请日：2020-10-13

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Anindya Nath ,  Zhiqing Li ,  Souvick Mitra ,  Alain Loiseau ,  Wei Liang

IPC: H02H9/04 ,  H01L27/02

Abstract: Embodiments of the disclosure provide an electrostatic discharge (ESD) device, including: an input pad; an underlapped field effect transistor (UL-FET) with a trigger voltage Vt, including: an underlapped drain region coupled to the input pad; a source region coupled to ground; and a gate structure coupled to the input pad; and a blocking layer separating the underlapped drain region from the gate structure of the UL-FET by an underlap distance.

公开(公告)号：US11955472B2

公开(公告)日：2024-04-09

申请号：US17554222

申请日：2021-12-17

Applicant: GlobalFoundries U.S. Inc.

Inventor： Meng Miao ,  Alain Loiseau ,  Souvick Mitra ,  Wei Liang ,  Robert J. Gauthier, Jr. ,  Anindya Nath

IPC: H01L27/02 ,  H01L27/12 ,  H01L29/74

CPC classification number: H01L27/0248 ,  H01L27/1207 ,  H01L29/7436

Abstract: Disclosed are embodiments of a semiconductor structure that includes a semiconductor-controlled rectifier (e.g., for electrostatic discharge (ESD) protection). The SCR can be readily integrated into advanced semiconductor-on-insulator processing technology platforms (e.g., a fully depleted silicon-on-insulator (FDSOI) processing technology platform) that employ hybrid semiconductor substrates (i.e., semiconductor substrates with both bulk semiconductor and semiconductor-on-insulator regions) and is configured with an on-Pwell semiconductor-on-insulator gate structure that is tied to an anode terminal to effectively lower the SCR trigger voltage. To further lower the trigger voltage of the SCR, the Pwell on which the gate structure sits may be made narrower than the gate structure and/or the doping profile of the Pwell on which the gate structure sits may be graded (e.g., P to P− closer to insulator layer). Additionally, to minimize parasitic capacitance, the gate structure may be shorter in length than contact regions parallel and adjacent thereto.

公开(公告)号：US20230395714A1

公开(公告)日：2023-12-07

申请号：US17831496

申请日：2022-06-03

Applicant: GlobalFoundries U.S. Inc.

Inventor： Anindya Nath ,  Alain Loiseau ,  Rajendran Krishnasamy

IPC: H01L29/78 ,  H01L21/8238 ,  H01L29/66

CPC classification number: H01L29/7835 ,  H01L21/823892 ,  H01L29/66659

Abstract: Device structures with an isolation well and methods of forming a device structure with an isolation well. The structure comprises a first well of a first conductivity type in a semiconductor substrate, and a second well of a second conductivity type in the semiconductor substrate. The second conductivity type is opposite to the first conductivity type. The first well includes a plurality of segments, and the second well is positioned in a vertical direction between the segments of the first well and a top surface of the semiconductor substrate.