公开(公告)号：US20240128322A1

公开(公告)日：2024-04-18

申请号：US17968404

申请日：2022-10-18

Applicant: GlobalFoundries U.S. Inc.

Inventor： George R. MULFINGER

IPC: H01L29/10 ,  H01L21/762 ,  H01L21/84 ,  H01L27/12 ,  H01L29/16

CPC classification number: H01L29/1054 ,  H01L21/76267 ,  H01L21/76283 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/16

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to a device with a laterally graded channel region and methods of manufacture. The structure includes a PFET region with a laterally graded semiconductor channel region under a gate material.

公开(公告)号：US20240234425A1

公开(公告)日：2024-07-11

申请号：US18095746

申请日：2023-01-11

Applicant: GlobalFoundries U.S. Inc.

Inventor： Tamilmani ETHIRAJAN ,  Kaustubh SHANBHAG ,  George R. MULFINGER ,  Anton V. TOKRANOV ,  Eric S. KOZARSKY ,  Hui ZHAN

IPC: H01L27/12 ,  H01L21/84 ,  H01L23/535 ,  H01L29/78

CPC classification number: H01L27/1203 ,  H01L21/84 ,  H01L23/535 ,  H01L29/7838

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to devices with isolation structures in active regions and methods of manufacture. The structure includes: an active region; a plurality of isolation structures within the active region; a plurality of gate structures overlapping the plurality of isolation structures within the active region; and diffusion regions on sides of the plurality of gate structures and the plurality of isolation structures.

公开(公告)号：US20230146952A1

公开(公告)日：2023-05-11

申请号：US17521076

申请日：2021-11-08

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： George R. MULFINGER ,  Matthew W. STOKER ,  Ryan W. SPORER ,  Man GU

IPC: H01L29/417 ,  H01L29/16

CPC classification number: H01L29/41783 ,  H01L29/1608

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to transistors with faceted raised source/drain regions and methods of manufacture. The structure includes: a substrate; a gate structure on the substrate; and faceted, raised source/drain regions adjacent to the gate structure and including at least two different semiconductor materials.