公开(公告)号：US20210193573A1

公开(公告)日：2021-06-24

申请号：US16726497

申请日：2019-12-24

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Nicholas LiCausi ,  Julien Frougier ,  Keith Donegan ,  Hyung Woo Kim

IPC: H01L23/528 ,  H01L23/522 ,  H01L23/532 ,  H01L27/24 ,  H01L27/22 ,  H01L27/11587 ,  H01L27/1159 ,  H01L43/02 ,  H01L43/08 ,  H01L43/12 ,  H01L45/00

Abstract: One illustrative device disclosed herein includes a layer of insulating material with its upper surface positioned at a first level and a recessed conductive interconnect structure positioned at least partially within the layer of insulating material, wherein a recessed upper surface of the recessed conductive interconnect structure is positioned at a second level that is below the first level. In this example, the device also includes a conductive cap layer positioned on the recessed upper surface of the recessed conductive interconnect structure, wherein an upper surface of the conductive cap layer is substantially co-planar with the upper surface of the layer of insulating material and a memory cell positioned above the conductive cap layer, wherein the memory cell comprises a lower conductive material that is conductively coupled to the conductive cap layer.

公开(公告)号：US20210193584A1

公开(公告)日：2021-06-24

申请号：US16726447

申请日：2019-12-24

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Nicholas LiCausi ,  Julien Frougier ,  Keith Donegan ,  Hyung Woo Kim

IPC: H01L23/532 ,  H01L23/522 ,  H01L23/528 ,  G11C5/06 ,  H01L21/768

Abstract: One illustrative device disclosed herein includes a layer of insulating material having an upper surface positioned at a first level and a recessed conductive interconnect structure positioned at least partially within the layer of insulating material, wherein the recessed conductive interconnect structure has a recessed upper surface that is positioned at a second level that is below the first level. In this example, the device also includes a recess defined in the recessed conductive interconnect structure, a memory cell positioned above the recessed conductive interconnect structure and a conductive via plug that is conductively coupled to the recessed conductive interconnect structure and a lower conductive material of the memory cell, wherein at least a portion of the conductive via plug is positioned in the recess defined in the recessed conductive interconnect.

公开(公告)号：US11158574B2

公开(公告)日：2021-10-26

申请号：US16726497

申请日：2019-12-24

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Nicholas LiCausi ,  Julien Frougier ,  Keith Donegan ,  Hyung Woo Kim

IPC: H01L23/528 ,  H01L45/00 ,  H01L23/532 ,  H01L27/24 ,  H01L27/22 ,  H01L27/11587 ,  H01L27/1159 ,  H01L43/02 ,  H01L43/08 ,  H01L43/12 ,  H01L23/522

Abstract: One illustrative device disclosed herein includes a layer of insulating material with its upper surface positioned at a first level and a recessed conductive interconnect structure positioned at least partially within the layer of insulating material, wherein a recessed upper surface of the recessed conductive interconnect structure is positioned at a second level that is below the first level. In this example, the device also includes a conductive cap layer positioned on the recessed upper surface of the recessed conductive interconnect structure, wherein an upper surface of the conductive cap layer is substantially co-planar with the upper surface of the layer of insulating material and a memory cell positioned above the conductive cap layer, wherein the memory cell comprises a lower conductive material that is conductively coupled to the conductive cap layer.

公开(公告)号：US11121087B2

公开(公告)日：2021-09-14

申请号：US16726447

申请日：2019-12-24

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Nicholas LiCausi ,  Julien Frougier ,  Keith Donegan ,  Hyung Woo Kim

IPC: H01L23/522 ,  H01L23/532 ,  H01L21/768 ,  H01L23/528 ,  G11C5/06

Abstract: One illustrative device disclosed herein includes a layer of insulating material having an upper surface positioned at a first level and a recessed conductive interconnect structure positioned at least partially within the layer of insulating material, wherein the recessed conductive interconnect structure has a recessed upper surface that is positioned at a second level that is below the first level. In this example, the device also includes a recess defined in the recessed conductive interconnect structure, a memory cell positioned above the recessed conductive interconnect structure and a conductive via plug that is conductively coupled to the recessed conductive interconnect structure and a lower conductive material of the memory cell, wherein at least a portion of the conductive via plug is positioned in the recess defined in the recessed conductive interconnect.