公开(公告)号：US20220181468A1

公开(公告)日：2022-06-09

申请号：US17116167

申请日：2020-12-09

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Shesh Mani Pandey ,  Judson Robert Holt

IPC: H01L29/66 ,  H01L27/12 ,  H01L29/78

Abstract: A transistor device formed on a semiconductor-on-insulator (SOI) substrate including a bulk semiconductor layer, a buried insulation (BOX) layer positioned on the bulk semiconductor layer, and an active semiconductor layer positioned on the BOX layer. The transistor device includes: a gate structure, a sidewall spacer, and a source/drain region; a plurality of distinct openings extending through the active semiconductor layer of the SOI substrate in the source/drain region adjacent the sidewall spacer, each opening of the plurality of openings extending to a respective recess formed in the BOX layer of the SOI substrate in the source/drain region adjacent the sidewall space, wherein each recess extends under a portion of the active semiconductor layer; and an epitaxial (epi) semiconductor material disposed in the recesses in the BOX layer, in the plurality of openings through the active semiconductor layer, and over a surface of the active semiconductor layer.

公开(公告)号：US11056591B2

公开(公告)日：2021-07-06

申请号：US16382184

申请日：2019-04-11

Applicant: GLOBALFOUNDRIES U.S. INC.

Inventor： Jin Wallner ,  Heng Yang ,  Judson Robert Holt

IPC: H01L21/8234 ,  H01L29/78 ,  H01L29/10 ,  H01L27/088 ,  H01L21/84

Abstract: A method of forming a semiconductor device is provided, which includes providing gate structures over an active region and forming a hard mask segment on the active region positioned between a first gate structure and a second gate structure. Cavities are formed in the active region using the gate structures and the hard mask segment as masking features, wherein each cavity has a width substantially equal to a minimum gate-to-gate spacing of the semiconductor device. Epitaxial material is grown in the cavities to form substantially uniform epitaxial structures in the active region.

公开(公告)号：US11043566B2

公开(公告)日：2021-06-22

申请号：US16599116

申请日：2019-10-10

Applicant: GLOBALFOUNDRIES U.S. INC.

Inventor： Jiehui Shu ,  Judson Robert Holt ,  Sipeng Gu ,  Haiting Wang

IPC: H01L29/423 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/417

Abstract: A semiconductor device is provided that includes a substrate, an active region, a pair of gates, a plurality of semiconductor structures and a plurality of pillar structures. The active region is over the substrate. The pair of gates is formed over the active region, and each gate of the pair of gates includes a gate structure and a pair of spacer structures disposed on sidewalls of the gate structure. The plurality of semiconductor structures is arranged between the pair of gates in an alternating arrangement configuration having a first width and a second width. The first width is substantially equal to a width of the gate structure. The plurality of semiconductor structures is separated by the plurality of pillar structures.

公开(公告)号：US20240258376A1

公开(公告)日：2024-08-01

申请号：US18161219

申请日：2023-01-30

Applicant: GlobalFoundries U.S. Inc.

Inventor： Judson Robert Holt ,  George Robert Mulfinger

IPC: H01L29/10 ,  H01L21/8238

CPC classification number: H01L29/1054 ,  H01L21/823807

Abstract: An integrated circuit (IC) device is disclosed which includes a first transistor over a substrate. The first transistor includes a gate over the substrate and between a source region and a drain region. The transistor further includes a first region of vertically-graded silicon germanium (“SiGe”) adjacent a first side of a channel under the gate, and a second region of vertically-graded SiGe adjacent a second side of the channel. The channel includes substantially uniformly-graded SiGe.

公开(公告)号：US11652142B2

公开(公告)日：2023-05-16

申请号：US17482374

申请日：2021-09-22

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Mankyu Yang ,  Richard Taylor, III ,  Alexander Derrickson ,  Alexander Martin ,  Jagar Singh ,  Judson Robert Holt ,  Haiting Wang

IPC: H01L29/08 ,  H01L29/66 ,  H01L29/735 ,  H01L29/10

CPC classification number: H01L29/0804 ,  H01L29/0808 ,  H01L29/0821 ,  H01L29/1008 ,  H01L29/6625 ,  H01L29/735

Abstract: A structure for a lateral bipolar junction transistor is provided. The structure comprising an emitter including a first concentration of a first dopant. A collector including a second concentration of the first dopant, the first concentration of the first dopant may be different from the second concentration of the first dopant. An intrinsic base may be laterally arranged between the emitter and the collector, and an extrinsic base region may be above the intrinsic base. An emitter extension may be arranged adjacent to the emitter, whereby the emitter extension laterally extends under a portion of the extrinsic base region. A halo region may be arranged adjacent to the emitter extension, whereby the halo region laterally extends under another portion of the extrinsic base region.