公开(公告)号：US11329158B2

公开(公告)日：2022-05-10

申请号：US16843421

申请日：2020-04-08

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Halting Wang ,  Judson R. Holt ,  Sipeng Gu

IPC: H01L21/00 ,  H01L29/78 ,  H01L29/66 ,  H01L21/02

Abstract: A structure for a field-effect transistor includes a semiconductor body, a first gate structure extending over the semiconductor body, and a second gate structure extending over the semiconductor body. A recess is in the semiconductor body between the first and second gate structures. A three part source/drain region includes a pair of spaced semiconductor spacers in the recess; a first semiconductor layer laterally between the pair of semiconductor spacers; and a second semiconductor layer over the first semiconductor layer. The pair of spaced semiconductor spacers, the first semiconductor layer and the second semiconductor layer may all have different dopant concentrations.

公开(公告)号：US11222844B2

公开(公告)日：2022-01-11

申请号：US16899543

申请日：2020-06-11

Applicant: GLOBALFOUNDRIES U.S. INC.

Inventor： Jun Lian ,  Sipeng Gu ,  Haiting Wang ,  Yanping Shen

IPC: H01L23/522 ,  H01L43/12 ,  H01L43/02 ,  H01L45/00 ,  H01L23/528 ,  H01L23/532 ,  H01L27/11585

Abstract: The present disclosure relates generally to structures in semiconductor devices and methods of forming the same. The present disclosure provides a semiconductor device including a first device region and a second device region. The first device region includes a first metal layer, a first via structure over the first metal layer, a second via structure over the first via structure, and a second metal layer over the second via structure. The first via structure and the second via structure electrically couple the second metal layer to the first metal layer. The second device region includes a third metal layer, a contact structure over the third metal layer, a memory cell structure over the contact structure, and a fourth metal layer over the memory cell structure. The first via structure and the contact structure are made of the same material.

公开(公告)号：US11177385B2

公开(公告)日：2021-11-16

申请号：US16781236

申请日：2020-02-04

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Haiting Wang ,  Sipeng Gu ,  Jiehui Shu ,  Baofu Zhu

IPC: H01L29/78 ,  H01L29/08 ,  H01L29/66

Abstract: Structures for a field-effect transistor and methods of forming a structure for a field-effect transistor. A gate structure extends over a channel region in a semiconductor body. The gate structure has a first side surface and a second side surface opposite the first side surface. A first source/drain region is positioned adjacent to the first side surface of the gate structure and a second source/drain region is positioned adjacent to the second side surface of the gate structure. The first source/drain region includes a first epitaxial semiconductor layer, and the second source/drain region includes a second epitaxial semiconductor layer. A first top surface of the first epitaxial semiconductor layer is positioned at a first distance from the channel region, a second top surface of the second epitaxial semiconductor layer is positioned at a second distance from the channel region, and the first distance is greater than the second distance.

公开(公告)号：US11127834B2

公开(公告)日：2021-09-21

申请号：US16599684

申请日：2019-10-11

Applicant: GLOBALFOUNDRIES U.S. INC.

Inventor： Jiehui Shu ,  Sipeng Gu ,  Halting Wang

IPC: H01L29/49 ,  H01L29/66 ,  H01L27/088 ,  H01L29/78 ,  H01L29/40

Abstract: The present disclosure generally relates to semiconductor structures and, more particularly, to gate structures and methods of manufacture. The method includes: forming a first gate structure and a second gate structure with gate materials; etching the gate materials within the second gate structure to form a trench; and depositing a conductive material within the trench so that the second gate structure has a metal composition different than the first gate structure.

公开(公告)号：US11908857B2

公开(公告)日：2024-02-20

申请号：US16901417

申请日：2020-06-15

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Yanping Shen ,  Haiting Wang ,  Sipeng Gu

IPC: H01L27/088 ,  H01L21/8234 ,  H01L21/8238

CPC classification number: H01L27/0886 ,  H01L21/823437 ,  H01L21/823468 ,  H01L21/823481 ,  H01L21/823878

Abstract: Structures for a semiconductor device that include dielectric isolation and methods of forming a structure for a semiconductor device that includes dielectric isolation. A semiconductor body includes a cavity, first and second gate structures extending over the semiconductor body, and a semiconductor layer including first and second sections on the semiconductor body. The first section of the semiconductor layer is laterally positioned between the cavity and the first gate structure, and the second section on the semiconductor layer is laterally positioned between the cavity and the second gate structure. An isolation structure is laterally positioned between the first and second sections of the semiconductor layer. The isolation structure includes a dielectric layer and a sidewall spacer having first and second sections. The dielectric layer includes a first portion in the cavity and a second portion between the first and second sections of the sidewall spacer.

公开(公告)号：US20210399126A1

公开(公告)日：2021-12-23

申请号：US16906490

申请日：2020-06-19

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Sipeng Gu ,  Judson R. Holt ,  Haiting Wang ,  Yanping Shen

IPC: H01L29/78 ,  H01L29/08 ,  H01L29/06 ,  H01L29/66

Abstract: An illustrative transistor device disclosed herein includes a gate structure positioned around a portion of a fin defined in a semiconductor substrate and epitaxial semiconductor material positioned on the fin in a source/drain region of the transistor device, wherein the epitaxial semiconductor material has a plurality of lower angled surfaces. In this example, the device further includes a first sidewall spacer positioned adjacent the gate structure, wherein a first portion of the first sidewall spacer is also positioned on and in physical contact with at least a portion of the lower angled surfaces of the epitaxial semiconductor material.

公开(公告)号：US20210336126A1

公开(公告)日：2021-10-28

申请号：US16855745

申请日：2020-04-22

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Yanping Shen ,  Haiting Wang ,  Sipeng Gu

IPC: H01L43/02 ,  H01L27/24 ,  H01L27/22 ,  H01L27/1159 ,  H01L43/08 ,  H01L43/10 ,  H01L43/12 ,  H01L45/00

Abstract: An illustrative device disclosed herein includes at least one layer of insulating material, a conductive contact structure having a conductive line portion and a conductive via portion and a memory cell positioned in a first opening in the at least one layer of insulating material. In this illustrative example, the memory cell includes a bottom electrode, a memory state material positioned above the bottom electrode and an internal sidewall spacer positioned within the first opening and above at least a portion of the memory state material, wherein the internal sidewall spacer defines a spacer opening and wherein the conductive via portion is positioned within the spacer opening and above a portion of the memory state material.

公开(公告)号：US11114466B2

公开(公告)日：2021-09-07

申请号：US16774087

申请日：2020-01-28

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Sipeng Gu ,  Jiehui Shu ,  Haiting Wang

IPC: H01L27/12 ,  H01L21/762 ,  H01L21/306 ,  H01L21/84 ,  H01L21/265 ,  H01L21/76

Abstract: One illustrative IC product disclosed herein includes an (SOI) substrate comprising a base semiconductor layer, a buried insulation layer and an active semiconductor layer positioned above the buried insulation layer. In this particular example, the IC product also includes a first region of localized high resistivity formed in the base semiconductor layer, wherein the first region of localized high resistivity has an electrical resistivity that is greater than an electrical resistivity of the material of the base semiconductor layer. The IC product also includes a first region comprising integrated circuits formed above the active semiconductor layer, wherein the first region comprising integrated circuits is positioned vertically above the first region of localized high resistivity in the base semiconductor layer.

公开(公告)号：US11004748B2

公开(公告)日：2021-05-11

申请号：US16432899

申请日：2019-06-05

Applicant: GLOBALFOUNDRIES U.S. INC.

Inventor： Sipeng Gu ,  Jiehui Shu ,  Haiting Wang

IPC: H01L21/8234 ,  H01L29/423 ,  H01L29/10 ,  H01L27/088

Abstract: This disclosure relates to a method of fabricating semiconductor devices with a gate-to-gate spacing that is wider than a minimum gate-to-gate spacing and the resulting semiconductor devices. The method includes forming gate structures over an active structure, the gate structures including a first gate structure, a second gate structure, and a third gate structure. The second gate structure is between the first and third gate structures. A plurality of epitaxial structures are formed adjacent to the gate structures, wherein the second gate structure separates two epitaxial structures and the two epitaxial structures are between the first and third gate structures. The second gate structure is removed. A conductive region is formed to connect the epitaxial structures between the first and third gate structures.

公开(公告)号：US11721728B2

公开(公告)日：2023-08-08

申请号：US16777531

申请日：2020-01-30

Applicant: GLOBALFOUNDRIES U.S. INC.

Inventor： Sipeng Gu ,  Jiehui Shu ,  Halting Wang ,  Yanping Shen

IPC: H01L29/417 ,  H01L29/78

CPC classification number: H01L29/41775 ,  H01L29/41791 ,  H01L29/7851

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to self-aligned contacts and methods of manufacture. The structure includes: adjacent diffusion regions located within a substrate material; sidewall structures above an upper surface of the substrate material, aligned on sides of the adjacent diffusion regions; and a contact between the sidewall structures and extending to within the substrate material between and in electrical contact with the adjacent diffusion regions.