公开(公告)号：US11934021B2

公开(公告)日：2024-03-19

申请号：US17649191

申请日：2022-01-27

Applicant: GlobalFoundries U.S. Inc.

Inventor： Hemant Martand Dixit ,  William J. Taylor, Jr. ,  Yusheng Bian ,  Theodore Letavic ,  Oscar D. Restrepo

IPC: G02B6/42 ,  G02B6/122 ,  G02B6/125 ,  G02B6/12

CPC classification number: G02B6/4269 ,  G02B6/122 ,  G02B6/125 ,  G02B2006/12135 ,  G02B2006/12142

Abstract: The disclosed subject matter relates to semiconductor devices for use in optoelectronic/photonic applications and integrated circuit (IC) chips. More particularly, the present disclosure relates to photonic devices having thermally conductive layers for the removal of heat from optoelectronic components in the photonic devices.

公开(公告)号：US20220028873A1

公开(公告)日：2022-01-27

申请号：US16935691

申请日：2020-07-22

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Oscar D. Restrepo ,  Edmund K. Banghart ,  William Taylor

IPC: H01L27/112 ,  H01L29/78 ,  H01L29/66

Abstract: Structures for an array of non-volatile memory cells and methods of forming a structure for an array of non-volatile memory cells. An active region of a substrate includes a first section having a side edge and a second section extending laterally from the side edge. The first section of the active region has a first length dimension in a direction parallel to the first side edge. The second section has a second length dimension in the direction parallel to the first side edge. The second length dimension is less than the first length dimension. A fin is positioned on the substrate in the second section of the active region. A gate structure extends over the fin and the second section of the active region.

公开(公告)号：US11538815B2

公开(公告)日：2022-12-27

申请号：US16935691

申请日：2020-07-22

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Oscar D. Restrepo ,  Edmund K. Banghart ,  William Taylor

IPC: H01L27/112 ,  H01L29/66 ,  H01L29/78 ,  H01L27/02 ,  H01L27/105 ,  H01L29/06

Abstract: Structures for an array of non-volatile memory cells and methods of forming a structure for an array of non-volatile memory cells. An active region of a substrate includes a first section having a side edge and a second section extending laterally from the side edge. The first section of the active region has a first length dimension in a direction parallel to the first side edge. The second section has a second length dimension in the direction parallel to the first side edge. The second length dimension is less than the first length dimension. A fin is positioned on the substrate in the second section of the active region. A gate structure extends over the fin and the second section of the active region.

公开(公告)号：US20240219636A1

公开(公告)日：2024-07-04

申请号：US18093039

申请日：2023-01-04

Applicant: GlobalFoundries U.S. Inc.

Inventor： Bartlomiej Jan Pawlak ,  Oscar D. Restrepo ,  Koushik Ramachandran ,  Yusheng Bian ,  Eduardo Cruz Silva

IPC: G02B6/122 ,  G02B6/13

CPC classification number: G02B6/1228 ,  G02B6/13 ,  G02B2006/12121

Abstract: Structures including an edge coupler and methods of forming such structures. The structure comprises a dielectric layer on a semiconductor substrate. The dielectric layer includes a cavity and an edge defining a boundary of the cavity. The structure further comprises an edge coupler including a waveguide core. The waveguide core includes a portion that extends past the edge of the dielectric layer and overhangs the cavity. The structure further comprises a heater positioned adjacent to the portion of the waveguide core. The heater is spaced by a gap from the portion of the waveguide core.