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    Chip module with robust in-package interconnects
    1.
    发明授权
    Chip module with robust in-package interconnects 有权

    公开(公告)号：US11804440B2

    公开(公告)日：2023-10-31

    申请号：US17160447

    申请日：2021-01-28

    Applicant: GLOBALFOUNDRIES U.S. Inc.

    Inventor： Saquib B. Halim ,  Frank G. Kuechenmeister ,  Kashi V Machani ,  Christian Goetze

    IPC: H01L23/538 ,  H01L23/00

    CPC classification number: H01L23/5384 ,  H01L23/5383 ,  H01L23/5386 ,  H01L24/14

    Abstract: Disclosed are chip module structures, each having a robust in-package interconnect for reliable performance. Some of the chip module structures achieve interconnect robustness through the use of vias in a spiral step pattern within the interconnect itself. Some chip module structures achieve interconnect robustness through the use of an interconnect stabilizer (referred to herein as a stabilization structure, fence or cage)), which includes vias in a repeating step pattern encircling the in-package interconnect, which is electrically isolated from back side solder balls, front side collapse chip connections (referred to herein as C4 connections), and the interconnect itself, and which is optionally connected to ground. Some chip module structures achieve interconnect robustness through the use of a combination of both vias in a spiral step pattern within the interconnect itself and an interconnect stabilizer.

    CHIP MODULE WITH ROBUST IN-PACKAGE INTERCONNECTS
    3.
    发明申请
    CHIP MODULE WITH ROBUST IN-PACKAGE INTERCONNECTS 有权

    公开(公告)号：US20220238448A1

    公开(公告)日：2022-07-28

    申请号：US17160447

    申请日：2021-01-28

    Applicant: GLOBALFOUNDRIES U.S. Inc.

    Inventor： Saquib B. Halim ,  Frank G. Kuechenmeister ,  Kashi V. Machani ,  Christian Goetze

    IPC: H01L23/538 ,  H01L23/00

    Abstract: Disclosed are chip module structures, each having a robust in-package interconnect for reliable performance. Some of the chip module structures achieve interconnect robustness through the use of vias in a spiral step pattern within the interconnect itself. Some chip module structures achieve interconnect robustness through the use of an interconnect stabilizer (referred to herein as a stabilization structure, fence or cage)), which includes vias in a repeating step pattern encircling the in-package interconnect, which is electrically isolated from back side solder balls, front side collapse chip connections (referred to herein as C4 connections), and the interconnect itself, and which is optionally connected to ground. Some chip module structures achieve interconnect robustness through the use of a combination of both vias in a spiral step pattern within the interconnect itself and an interconnect stabilizer.

    CRACKSTOP WITH EMBEDDED PASSIVE RADIO FREQUENCY NOISE SUPPRESSOR AND METHOD
    5.
    发明申请
    CRACKSTOP WITH EMBEDDED PASSIVE RADIO FREQUENCY NOISE SUPPRESSOR AND METHOD 有权

    公开(公告)号：US20220406732A1

    公开(公告)日：2022-12-22

    申请号：US17352414

    申请日：2021-06-21

    Applicant: GLOBALFOUNDRIES U.S. Inc.

    Inventor： Nicholas A. Polomoff ,  Frank G. Kuechenmeister ,  Richard F. Taylor, III ,  Saquib B. Halim

    IPC: H01L23/00 ,  H01L23/58 ,  H01L23/66 ,  H03H1/00 ,  G06F30/392

    Abstract: Disclosed is a radio frequency integrated circuit (RFIC) chip that includes an integrated circuit (IC) area and a crackstop laterally surrounding the IC area. The crackstop includes a metallic barrier (or, alternatively, concentric metallic barriers) electrically isolated from the IC area. One or more noise suppressors and, particularly, one or more passive filters (e.g., low pass filter(s), high pass filter(s), band pass filter(s), and/or band stop filter(s)) are integrated into the structure of the metallic barrier(s) to inhibit propagation, through the crackstop, of noise signals within a specific RF range. The specific RF range can be a customer-specified operating parameter. By embedding customized noise suppressor(s) into the crackstop, local signal interference unique to the customer-specified operating parameters can be minimized while also avoiding or at least minimizing the risk of moisture ingress to the IC area. Also disclosed is a method of forming the chip.

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