公开(公告)号：US12204144B2

公开(公告)日：2025-01-21

申请号：US17525327

申请日：2021-11-12

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Nicholas A. Polomoff ,  Yusheng Bian ,  Vibhor Jain

IPC: G01N27/04 ,  G02B6/12 ,  G02B6/122 ,  H01L23/00

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to a photonic chip security structure and methods of manufacture. The structure includes an optical component over a substrate material, and at least one vertical wall including a reflecting material within a dielectric stack of material and surrounding the optical component.

公开(公告)号：US20210356514A1

公开(公告)日：2021-11-18

申请号：US16872597

申请日：2020-05-12

Applicant: GLOBALFOUNDRIES U.S. INC.

Inventor： Nicholas A. Polomoff ,  Dewei Xu ,  Eric D. Hunt-Schroeder

IPC: G01R31/28

Abstract: Embodiments of the disclosure provide a crack detecting and monitoring system, including: a plurality of electrically conductive structures extending about a protective barrier formed in an inactive region of an integrated circuit (IC), wherein an active region of the IC is enclosed within the protective barrier; and a plurality of stages of sensing circuits connected in series for sensing a change in an electrical characteristic of each of the plurality of structures and for receiving an enable signal, wherein each sensing circuit is coupled to a respective structure of the plurality of structures, the change in the electrical characteristic indicating damage to the respective structure, wherein each sensing circuit incudes a circuit for selectively generating the enable signal for a next sensing circuit in the plurality of stages of sensing circuits.

公开(公告)号：US11815717B2

公开(公告)日：2023-11-14

申请号：US17525293

申请日：2021-11-12

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Vibhor Jain ,  Nicholas A. Polomoff ,  Yusheng Bian

IPC: G02B6/12 ,  G02B6/122 ,  G02B6/24 ,  H01L23/00

CPC classification number: G02B6/122 ,  G02B6/243 ,  H01L23/573 ,  G02B2006/12061 ,  G02B2006/12126

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to a photonic chip security structure and methods of manufacture. The structure includes an optical component and a photonic chip security structure having a vertical wall composed of light absorbing material surrounding the optical component.

公开(公告)号：US20230130467A1

公开(公告)日：2023-04-27

申请号：US17452129

申请日：2021-10-25

Applicant: GlobalFoundries U.S. Inc.

Inventor： Nicholas A. Polomoff ,  Thomas Houghton ,  Yusheng Bian

IPC: G02B6/12 ,  G02B6/42 ,  G02B6/30 ,  G02B6/43

Abstract: A photonic integrated circuit (PIC) die are provided. The PIC die includes a set of optical connect grooves including a first groove aligning a core of a first optical fiber positioned with a first optical component in a first layer at a first vertical depth in a plurality of layers of a body of the die, and a second groove aligning a core of a second optical fiber positioned therein with a second optical component in a second, different layer at a second different vertical depth in the plurality of layers. The grooves may also have end faces at different lateral depths from an edge of the body of the PIC die. Any number of the first and second grooves can be used to communicate an optical signal to any number of layers at different vertical and/or lateral depths within the body of the PIC die.

公开(公告)号：US11215661B2

公开(公告)日：2022-01-04

申请号：US16872597

申请日：2020-05-12

Applicant: GLOBALFOUNDRIES U.S. INC.

Inventor： Nicholas A. Polomoff ,  Dewei Xu ,  Eric D. Hunt-Schroeder

IPC: G01R31/28

Abstract: Embodiments of the disclosure provide a crack detecting and monitoring system, including: a plurality of electrically conductive structures extending about a protective barrier formed in an inactive region of an integrated circuit (IC), wherein an active region of the IC is enclosed within the protective barrier; and a plurality of stages of sensing circuits connected in series for sensing a change in an electrical characteristic of each of the plurality of structures and for receiving an enable signal, wherein each sensing circuit is coupled to a respective structure of the plurality of structures, the change in the electrical characteristic indicating damage to the respective structure, wherein each sensing circuit includes a circuit for selectively generating the enable signal for a next sensing circuit in the plurality of stages of sensing circuits.

公开(公告)号：US20210375788A1

公开(公告)日：2021-12-02

申请号：US17400847

申请日：2021-08-12

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Nicholas A. Polomoff ,  Jae Kyu Cho ,  Mohamed A. Rabie ,  Andreas D. Stricker

IPC: H01L23/00 ,  H01L23/522 ,  H01L31/02 ,  H01L33/62

Abstract: Structures for an optical fiber groove and methods of forming a structure for an optical fiber groove. A photonics chip includes a substrate and an interconnect structure over the substrate. The photonics chip has a first exterior corner, a second exterior corner, and a side edge extending from the first exterior corner to the second exterior corner. The substrate includes a groove positioned along the side edge between the first exterior corner and the second exterior corner. The groove is arranged to intersect the side edge at a groove corner, and the interconnect structure includes metal structures adjacent to the first groove corner. The metal structures extend diagonally in the interconnect structure relative to the side edge of the photonics chip.

公开(公告)号：US11145606B1

公开(公告)日：2021-10-12

申请号：US16830543

申请日：2020-03-26

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Nicholas A. Polomoff ,  Jae Kyu Cho ,  Mohamed A. Rabie ,  Andreas D. Stricker

IPC: H01L23/00 ,  H01L23/522 ,  H01L31/02 ,  H01L33/62

Abstract: Structures for an optical fiber groove and methods of forming a structure for an optical fiber groove. A photonics chip includes a substrate and an interconnect structure over the substrate. The photonics chip has a first exterior corner, a second exterior corner, and a side edge extending from the first exterior corner to the second exterior corner. The substrate includes a groove positioned along the side edge between the first exterior corner and the second exterior corner. The groove is arranged to intersect the side edge at a groove corner, and the interconnect structure includes metal structures adjacent to the first groove corner. The metal structures extend diagonally in the interconnect structure relative to the side edge of the photonics chip.

公开(公告)号：US20240402421A1

公开(公告)日：2024-12-05

申请号：US18802210

申请日：2024-08-13

Applicant: GlobalFoundries U.S. Inc.

Inventor： Nicholas A. Polomoff ,  Thomas Houghton ,  Yusheng Bian

IPC: G02B6/12 ,  G02B6/30 ,  G02B6/42 ,  G02B6/43

Abstract: A photonic integrated circuit (PIC) die are provided. The PIC die includes a set of optical connect grooves including a first groove aligning a core of a first optical fiber positioned with a first optical component in a first layer at a first vertical depth in a plurality of layers of a body of the die, and a second groove aligning a core of a second optical fiber positioned therein with a second optical component in a second, different layer at a second different vertical depth in the plurality of layers. The grooves may also have end faces at different lateral depths from an edge of the body of the PIC die. Any number of the first and second grooves can be used to communicate an optical signal to any number of layers at different vertical and/or lateral depths within the body of the PIC die.

公开(公告)号：US20240030160A1

公开(公告)日：2024-01-25

申请号：US18479230

申请日：2023-10-02

Applicant: GlobalFoundries U.S. Inc.

Inventor： Nicholas A. Polomoff ,  Frank G. Kuechenmeister ,  Richard F. Taylor, III ,  Saquib B. Halim

IPC: H01L23/00 ,  G06F30/392 ,  H01L23/66 ,  H03H1/00 ,  H01L23/58

CPC classification number: H01L23/562 ,  H01L23/564 ,  G06F30/392 ,  H01L23/66 ,  H03H1/0007 ,  H01L23/585

Abstract: Disclosed is a radio frequency integrated circuit (RFIC) chip that includes an integrated circuit (IC) area and a crackstop laterally surrounding the IC area. The crackstop includes a metallic barrier (or, alternatively, concentric metallic barriers) electrically isolated from the IC area. One or more noise suppressors and, particularly, one or more passive filters (e.g., low pass filter(s), high pass filter(s), band pass filter(s), and/or band stop filter(s)) are integrated into the structure of the metallic barrier(s) to inhibit propagation, through the crackstop, of noise signals within a specific RF range. The specific RF range can be a customer-specified operating parameter. By embedding customized noise suppressor(s) into the crackstop, local signal interference unique to the customer-specified operating parameters can be minimized while also avoiding or at least minimizing the risk of moisture ingress to the IC area. Also disclosed is a method of forming the chip.

公开(公告)号：US11740418B2

公开(公告)日：2023-08-29

申请号：US17209416

申请日：2021-03-23

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Nicholas A. Polomoff ,  John J. Ellis-Monaghan ,  Frank G. Kuechenmeister ,  Jae Kyu Cho ,  Michal Rakowski

IPC: G02B6/42 ,  H01L23/00 ,  G02B6/30 ,  G02B6/12

CPC classification number: G02B6/4248 ,  G02B6/30 ,  H01L23/562 ,  G02B2006/12119

Abstract: Embodiments of the disclosure provide a photonic integrated circuit (PIC) structure with a passage for a waveguide through a barrier structure. The PIC structure includes a barrier structure on a substrate, having a first sidewall and a second sidewall opposite the first sidewall. A passage is within the barrier structure, and extends from a first end at the first sidewall of the barrier structure to a second end at the second sidewall of the barrier structure. A shape of the passage includes a reversal segment between the first end and the second end. A waveguide within the passage and extends from the first end to the second end of the barrier structure.