公开(公告)号：US20250078913A1

公开(公告)日：2025-03-06

申请号：US18459530

申请日：2023-09-01

Applicant: GlobalFoundries U.S. Inc.

Inventor： Xuemei Hui ,  Shafiullah Syed ,  Qiao Yang ,  Wei Zhao

IPC: G11C11/412 ,  G11C11/419 ,  H10B10/00

Abstract: A static random access memory (SRAM) cell includes P-type and N-type transistors having secondary gates. A node connected to all secondary gates receives a write enable signal (WEN). A low WEN forward biases the P-type transistors and increases the toggle threshold voltage (Vtth) of the SRAM cell to avoid data switching during a read. A high WEN forward biases the N-type transistors and decreases Vtth during a write. The SRAM cell can be implemented using a fully depleted semiconductor-on-insulator technology, where the secondary gates include corresponding portions of a well region below. In this case, an array of SRAM cells can be above a single well region. Alternatively, the array can be sectioned into sub-arrays above different well regions and a decoder can output sub-array-specific WENs to the different well regions (e.g., with only one WEN being high at a given time to reduce capacitance).

公开(公告)号：US12046670B2

公开(公告)日：2024-07-23

申请号：US17488235

申请日：2021-09-28

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Zhixing Zhao ,  Manjunatha Prabhu ,  Shafiullah Syed

IPC: H01L29/78 ,  H01L29/40 ,  H01L29/417 ,  H01L29/423

CPC classification number: H01L29/78 ,  H01L29/401 ,  H01L29/41775 ,  H01L29/4238 ,  H01L29/41783

Abstract: A semiconductor device comprising an active region, and a gate having side portions and a middle portion, whereby the middle portion is arranged between the side portions. The side portions and the middle portion of the gate may be arranged over the active region. The middle portion may be horizontally wider than the side portions. A first gate contact may be arranged over the middle portion.