公开(公告)号：US20230147981A1

公开(公告)日：2023-05-11

申请号：US18149239

申请日：2023-01-03

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： David Pritchard ,  Heng Yang ,  Hongru Ren ,  Neha Nayyar ,  Manjunatha Prabhu ,  Elizabeth Strehlow ,  Salvatore Cimino

IPC: H01L29/76 ,  H01L29/08 ,  H01L29/10

CPC classification number: H01L29/7606 ,  H01L29/0847 ,  H01L29/1033

Abstract: A planar transistor device is disclosed including a gate structure positioned above a semiconductor substrate, the semiconductor substrate comprising a substantially planar upper surface, a channel region, a source region, a drain region, and at least one layer of a two-dimensional (2D) material that is positioned in at least one of the source region, the drain region or the channel region, wherein the layer of 2D material has a substantially planar upper surface, a substantially planar bottom surface and a substantially uniform vertical thickness across an entire length of the layer of 2D material in the gate length direction and across an entire width of the layer of 2D material in the gate width direction, wherein the substantially planar upper surface and the substantially planar bottom surface of the layer of 2D material are positioned approximately parallel to a substantially planar surface of the semiconductor substrate.

公开(公告)号：US11581430B2

公开(公告)日：2023-02-14

申请号：US16548518

申请日：2019-08-22

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： David Pritchard ,  Heng Yang ,  Hongru Ren ,  Neha Nayyar ,  Manjunatha Prabhu ,  Elizabeth Strehlow ,  Salvatore Cimino

IPC: H01L29/06 ,  H01L31/00 ,  H01L29/76 ,  H01L29/08 ,  H01L29/10

Abstract: A planar transistor device is disclosed including a gate structure positioned above a semiconductor substrate, the semiconductor substrate comprising a substantially planar upper surface, a channel region, a source region, a drain region, and at least one layer of a two-dimensional (2D) material that is positioned in at least one of the source region, the drain region or the channel region, wherein the layer of 2D material has a substantially planar upper surface, a substantially planar bottom surface and a substantially uniform vertical thickness across an entire length of the layer of 2D material in the gate length direction and across an entire width of the layer of 2D material in the gate width direction, wherein the substantially planar upper surface and the substantially planar bottom surface of the layer of 2D material are positioned approximately parallel to a substantially planar surface of the semiconductor substrate.

公开(公告)号：US11177182B2

公开(公告)日：2021-11-16

申请号：US16776636

申请日：2020-01-30

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Heng Yang ,  David Pritchard ,  Kai Sun ,  Hongru Ren ,  Neha Nayyar ,  Manjunatha Prabhu ,  Elizabeth Strehlow ,  Salvatore Cimino

IPC: H01L29/66 ,  H01L21/8238

Abstract: One illustrative vertical transistor device disclosed herein includes a channel region comprising at least one layer of a two-dimensional (2D) material, a bottom source/drain region, a top source/drain region and a gate structure positioned all around at least the at least one layer of a two-dimensional (2D) material.

公开(公告)号：US20210242094A1

公开(公告)日：2021-08-05

申请号：US16776636

申请日：2020-01-30

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Heng Yang ,  David Pritchard ,  Kai Sun ,  Hongru Ren ,  Neha Nayyar ,  Manjunatha Prabhu ,  Elizabeth Strehlow ,  Salvatore Cimino

IPC: H01L21/8238

Abstract: One illustrative vertical transistor device disclosed herein includes a channel region comprising at least one layer of a two-dimensional (2D) material, a bottom source/drain region, a top source/drain region and a gate structure positioned all around at least the at least one layer of a two-dimensional (2D) material.

公开(公告)号：US20210242316A1

公开(公告)日：2021-08-05

申请号：US16776711

申请日：2020-01-30

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Heng Yang ,  David Pritchard ,  Kai Sun ,  Hongru Ren ,  Neha Nayyar ,  Manjunatha Prabhu ,  Elizabeth Strehlow ,  Salvatore Cimino

IPC: H01L29/417 ,  H01L29/16 ,  H01L29/08 ,  H01L29/78 ,  H01L29/66

Abstract: One illustrative device disclosed herein includes a bottom source/drain region and a top source/drain region positioned vertically above at least a portion of the bottom source/drain region, wherein each of the bottom source/drain region and the top source/drain region comprise at least one layer of a two-dimensional (2D) material. The device also includes a substantially vertically oriented semiconductor structure positioned vertically between the bottom source/drain region and the top source/drain region and a gate structure positioned all around an outer perimeter of the substantially vertically oriented semiconductor structure for at least a portion of the vertical height of the substantially vertically oriented semiconductor structure.

公开(公告)号：US12046670B2

公开(公告)日：2024-07-23

申请号：US17488235

申请日：2021-09-28

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Zhixing Zhao ,  Manjunatha Prabhu ,  Shafiullah Syed

IPC: H01L29/78 ,  H01L29/40 ,  H01L29/417 ,  H01L29/423

CPC classification number: H01L29/78 ,  H01L29/401 ,  H01L29/41775 ,  H01L29/4238 ,  H01L29/41783

Abstract: A semiconductor device comprising an active region, and a gate having side portions and a middle portion, whereby the middle portion is arranged between the side portions. The side portions and the middle portion of the gate may be arranged over the active region. The middle portion may be horizontally wider than the side portions. A first gate contact may be arranged over the middle portion.

公开(公告)号：US20220285274A1

公开(公告)日：2022-09-08

申请号：US17194565

申请日：2021-03-08

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Hongru Ren ,  David Pritchard ,  Ryan W. Sporer ,  Manjunatha Prabhu

IPC: H01L23/535 ,  H01L27/12 ,  H01L21/74

Abstract: An illustrative device disclosed herein includes a doped well region and a conductive well tap conductively coupled to the doped well region, the conductive well tap including first and second opposing sidewall surfaces. In this example the device also includes a first sidewall spacer that has a first vertical height positioned around the conductive well tap and a second sidewall spacer positioned adjacent the first sidewall spacer along the first and second opposing sidewall surfaces of the conductive well tap, wherein the second sidewall spacer has a second vertical height that is less than the first vertical height.

公开(公告)号：US11610843B2

公开(公告)日：2023-03-21

申请号：US17194565

申请日：2021-03-08

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Hongru Ren ,  David Pritchard ,  Ryan W. Sporer ,  Manjunatha Prabhu

IPC: H01L23/535 ,  H01L21/74 ,  H01L27/12

Abstract: An illustrative device disclosed herein includes a doped well region and a conductive well tap conductively coupled to the doped well region, the conductive well tap including first and second opposing sidewall surfaces. In this example the device also includes a first sidewall spacer that has a first vertical height positioned around the conductive well tap and a second sidewall spacer positioned adjacent the first sidewall spacer along the first and second opposing sidewall surfaces of the conductive well tap, wherein the second sidewall spacer has a second vertical height that is less than the first vertical height.

公开(公告)号：US11094791B1

公开(公告)日：2021-08-17

申请号：US16776711

申请日：2020-01-30

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Heng Yang ,  David Pritchard ,  Kai Sun ,  Hongru Ren ,  Neha Nayyar ,  Manjunatha Prabhu ,  Elizabeth Strehlow ,  Salvatore Cimino

IPC: H01L29/47 ,  H01L29/417 ,  H01L29/16 ,  H01L29/66 ,  H01L29/78 ,  H01L29/08

Abstract: One illustrative device disclosed herein includes a bottom source/drain region and a top source/drain region positioned vertically above at least a portion of the bottom source/drain region, wherein each of the bottom source/drain region and the top source/drain region comprise at least one layer of a two-dimensional (2D) material. The device also includes a substantially vertically oriented semiconductor structure positioned vertically between the bottom source/drain region and the top source/drain region and a gate structure positioned all around an outer perimeter of the substantially vertically oriented semiconductor structure for at least a portion of the vertical height of the substantially vertically oriented semiconductor structure.