公开(公告)号：US20220201408A1

公开(公告)日：2022-06-23

申请号：US17643241

申请日：2021-12-08

Applicant: GN Audio A/S

Inventor： Erling SKJOLDBORG ,  Brian Dam PEDERSEN ,  Leo Larsen ,  Bo SCHMIDT

IPC: H04R25/00

Abstract: An electronic device is configured for facilitating call communication with at least one hearing device is provided, Additionally, a method for call communication with at least one hearing device, and a hearing device is provided. The electronic device comprises a first interface for interconnecting with a call communication software, e.g. via a call protocol, and an interacting unit configured for interacting with the hearing device. The interacting unit is configured for obtaining an audio encryption key and transmitting/presenting the audio encryption key to the hearing device. The electronic device further comprises a transmission unit configured for broadcasting encrypted audio during a call facilitated by the call communication software, the audio being encrypted using the audio encryption key. The audio encryption key may be configured to be valid for a duration of the call.

公开(公告)号：US20210084413A1

公开(公告)日：2021-03-18

申请号：US17054691

申请日：2018-06-01

Applicant: Erling SKJOLDBORG ,  GN Audio A/S

Inventor： Erling SKJOLDBORG

IPC: H04R5/033 ,  H04R5/04 ,  H04R1/10 ,  H04R1/08 ,  H03M1/12 ,  H03M1/66

Abstract: A headset system comprising a headset, which headset comprises at least a first earphone, a D/A converter, a first cable and a first connector. The headset system further comprises a control box, which control box comprises a second connecter, which is adapted to be connected to the first connector, and a third connector which is adapted to be connected to a fourth connector of a computing device. The control box comprises a user interface. The D/A converter is arranged at the headset and the control box is adapted to send control signals via the first cable to the headset, when the user interface is activated by a user.

公开(公告)号：US20180188768A1

公开(公告)日：2018-07-05

申请号：US15840565

申请日：2017-12-13

Applicant: GN Audio A/S

Inventor： Erling SKJOLDBORG

IPC: G06F1/06 ,  H04R3/00 ,  G06F13/362

CPC classification number: G06F1/06 ,  G06F13/362 ,  G06F13/4269 ,  G06F13/4273 ,  H04R3/00 ,  H04R2420/07

Abstract: The invention concerns an apparatus comprising multiple processors, such as microprocessors, that communicate with each other. The claimed apparatus provides communication between two or more processors, such as microprocessors, and enables efficient half-duplex two-way communication between two processors, each having only two logic output pins and two logic input pins, e.g. GPIO pins, available for the communication.The apparatus (109) comprises a first processor (101) and a second processor (102), each having a first logic output pin (11, 21), a second logic output pin (12, 22), a first logic input pin (13, 23) and a second logic input pin (14, 24). For each of the first and the second processor (101, 102), the first logic output pin (11, 21) is connected to the second logic input pin (14, 24) of the respective other processor (101, 102), and for each of the first and the second processor (101, 102), the second logic output pin (12, 22) is connected to the first logic input pin (13, 23) of the respective other processor (101, 102).Each of the first and the second processor (101, 102) is operable in a transmit mode (301) for transmitting data to the respective other processor (101, 102) by controlling the second logic output pin (12, 22) to provide a logic data signal (DAT) indicating a sequence of data bits (D7-D0) and controlling the first logic output pin (11, 21) to provide a logic clock signal (CLK) with state transitions indicating when the logic data signal (DAT) indicates the values of the individual data bits (D7-D0) in the sequence.Each of the first and the second processor (101, 102) is operable in a receive mode (401) for receiving data from the respective other processor (101, 102) by determining a sequence of data bits (D7-D0) from the logic data signal (DAT) received on the first logic input pin (13, 23) in response to state transitions of the logic clock signal (CLK) received on the second logic input pin (14, 24).The apparatus (109) is characterized in that each of the first and the second processor (101, 102) further is configured to: in dependence on being in the receive mode (401) and able to receive data, control the second logic output pin (12, 22) to provide a logic clear-to-send signal (CTS) indicating the ability to receive data and control the first logic output pin (11, 21) to provide a logic data-acknowledge signal (ACK) with state transitions indicating successful reception of individual data bits (D7-D0); and in dependence on being in the transmit mode (301), delay transmission of the first data bit (D7-D0) in the sequence until determining that the logic clear-to-send signal (CTS) indicates the ability to receive data by the respective other processor (101, 102) and delay transmission of each subsequent data bit (D7-D0) in the sequence until determining a state transition of the logic data-acknowledge signal (ACK) that indicates successful reception of the respective previous data bit (D7-D0) by the respective other processor (101, 102).

公开(公告)号：US20170318142A1

公开(公告)日：2017-11-02

申请号：US15496733

申请日：2017-04-25

Applicant: GN Audio A/S

Inventor： Erling SKJOLDBORG

IPC: H04M1/60 ,  H04W76/02 ,  H04M1/725 ,  H04R1/08 ,  H04W4/00

CPC classification number: H04M1/6066 ,  H04M1/2535 ,  H04M1/6008 ,  H04M1/72527 ,  H04M2250/02 ,  H04M2250/08 ,  H04R1/08 ,  H04R1/1041 ,  H04R1/1091 ,  H04R2201/107 ,  H04R2420/07 ,  H04W4/80 ,  H04W76/14

Abstract: A headset adapter and a headset system for voice communication comprising a headset and a headset adapter as well as a method of enabling microphone transmission to a host device are provided. The headset comprises at least one earphone having a headset speaker, a headset microphone and a headset transceiver, the headset adapter being configured to interconnect the headset and a host device, the headset adapter comprising an adapter processor, a host interface, such as a host interface interconnecting the adapter processor and the host device, an adapter transceiver configured to establish a wireless communication link with the headset. The adapter furthermore comprises a controller configured to enable and disable the headset microphone. The adapter processor is configured to receive a request for headset microphone activation or microphone deactivation, for example from the host interface, and in response to receiving the request providing a control signal to the controller to enable or disable the headset microphone. The controller may thus activate the transceiver to configure the wireless communication link with the headset.