公开(公告)号：US20120089870A1

公开(公告)日：2012-04-12

申请号：US12985348

申请日：2011-01-06

申请人： GUO-YI CHEN ,  HAI-QING ZHOU ,  JIAN-CHUN PAN

发明人： GUO-YI CHEN ,  HAI-QING ZHOU ,  JIAN-CHUN PAN

IPC分类号： G06F11/22 ,  G06F15/177

CPC分类号： G06F11/1417 ,  G06F11/1666

摘要： A BIOS refresh device includes a first socket, a second socket, and a jumper. The first socket includes a first elastic contact, a first voltage contact, and a first ground contact. The second socket includes a second elastic contact, a second voltage contact, and a second ground contact. The jumper includes a first pin, a second pin, a third pin, and a fourth pin. The first pin is electronically connected with the second elastic contact. The second pin is electronically connected with the first voltage contact or the second voltage contact. The third pin is electronically connected with the first elastic contact. The fourth pin is electronically connected with the second ground contact or the second ground contact.

摘要翻译： BIOS刷新装置包括第一插座，第二插座和跳线。 第一插座包括第一弹性触点，第一电压触点和第一接地触头。 第二插座包括第二弹性触点，第二电压触点和第二接地触点。 跳线包括第一引脚，第二引脚，第三引脚和第四引脚。 第一针与第二弹性触点电连接。 第二引脚与第一电压触点或第二电压触点电连接。 第三针与第一弹性触点电连接。 第四针与第二接地触点或第二接地触点电连接。

公开(公告)号：US20130059464A1

公开(公告)日：2013-03-07

申请号：US13277223

申请日：2011-10-20

申请人： JIAN-CHUN PAN ,  HAI-QING ZHOU ,  YI-XIN TU

发明人： JIAN-CHUN PAN ,  HAI-QING ZHOU ,  YI-XIN TU

IPC分类号： H01R11/00

CPC分类号： H01R31/06 ,  H01R24/58 ,  H01R2201/20

摘要： An audio test cable includes three types of audio input and output (I/O) ports. The input port and the output port in each type of audio I/O ports form a short circuit for carrying a loopback test for a motherboard. The audio test cable also includes a test audio jack which connects to the output port of all types of audio I/O ports for carrying out an audio-quality test for the motherboard.

摘要翻译： 音频测试电缆包括三种类型的音频输入和输出（I / O）端口。 每种类型的音频I / O端口的输入端口和输出端口构成一个短路，用于对主板进行环回测试。 音频测试电缆还包括连接到所有类型的音频I / O端口的输出端口的测试音频插孔，用于对主板进行音频质量测试。

公开(公告)号：US20130017707A1

公开(公告)日：2013-01-17

申请号：US13280297

申请日：2011-10-24

申请人： JIAN-CHUN PAN ,  HAI-QING ZHOU ,  YI-XIN TU

发明人： JIAN-CHUN PAN ,  HAI-QING ZHOU ,  YI-XIN TU

IPC分类号： H01R13/627

CPC分类号： H01R13/6273

摘要： A connector assembly includes a first connector and a second connector. The first connector includes a main body, and a latching member extending out from the main body. The latching member includes a resilient extending portion extending from an outer surface of the main body, and a latching protrusion extending out from the extending portion. The second connector to be connected to the first connector, and includes a base, and a connecting member extending out from an outer surface of the base. The connecting member defining sliding groove and a receiving portion communicating with the sliding groove for latching the latching protrusion. Wherein when the first and second connectors are being connected, the latching member slides through the sliding groove, such that the latching protrusion is latched in the receiving portion.

摘要翻译： 连接器组件包括第一连接器和第二连接器。 第一连接器包括主体和从主体延伸出的闩锁构件。 闩锁构件包括从主体的外表面延伸的弹性延伸部分和从延伸部分伸出的闩锁突起。 要连接到第一连接器的第二连接器，并且包括基座，以及从基座的外表面延伸出的连接构件。 所述连接构件限定滑动槽和与所述滑动槽连通以用于闩锁所述闩锁突起的接收部。 其中当第一和第二连接器被连接时，闩锁构件滑动通过滑动槽，使得闩锁突起被锁定在接收部分中。

公开(公告)号：US20120137036A1

公开(公告)日：2012-05-31

申请号：US12970956

申请日：2010-12-17

申请人： YUN-SHAN XIAO ,  JIAN-CHUN PAN ,  HAI-QING ZHOU

发明人： YUN-SHAN XIAO ,  JIAN-CHUN PAN ,  HAI-QING ZHOU

IPC分类号： H05K7/10

CPC分类号： G06F8/66 ,  G06F1/24

摘要： A basic input output system (BIOS) refresh apparatus includes a jumper device, which includes a first pin, a second pin connected to a power source through a resistor, a third pin, and a grounded fourth pin. A master BIOS socket includes a voltage pin connected to the power source and a signal pin connected to the first pin of the jumper device. A slave BIOS socket includes a voltage pin connected to the power source and a signal pin connected to the third pin of the jumper device. Other pins of the master BIOS socket are correspondingly connected to other pins of the slave BIOS socket. The signal pin of the master BIOS socket or the slave BIOS socket receives high level signal to make a corresponding BIOS chip mounted thereon work when the first or third pin is connected to the second pin of the jumper device.

摘要翻译： 基本输入输出系统（BIOS）刷新装置包括跳线装置，其包括第一引脚，通过电阻连接到电源的第二引脚，第三引脚和接地的第四引脚。 主BIOS插座包括连接到电源的电压引脚和连接到跳线器件的第一引脚的信号引脚。 辅助BIOS插座包括连接到电源的电压引脚和连接到跳线器件的第三引脚的信号引脚。 主BIOS插座的其他引脚相应地连接到从BIOS插槽的其他引脚。 主BIOS插座或从BIOS插座的信号引脚接收高电平信号，使得当第一或第三引脚连接到跳线器件的第二引脚时，其上安装有相应的BIOS芯片工作。

公开(公告)号：US20130043896A1

公开(公告)日：2013-02-21

申请号：US13271247

申请日：2011-10-12

申请人： JIAN-CHUN PAN ,  HAI-QING ZHOU ,  YI-XIN TU

发明人： JIAN-CHUN PAN ,  HAI-QING ZHOU ,  YI-XIN TU

IPC分类号： G01R31/00

CPC分类号： G01R31/2806

摘要： A test device for testing a printed circuit board (PCB) includes a base and a measuring device. The measuring device includes a testing pin and is capable of measuring any desired point of the PCB on condition that the pin makes contact with the point at an included angle between the pin and a back surface of the PCB which is larger than a predetermined angle. The distance between the base and the PCB satisfies: H>L tan θ, where H is the vertical distance between the PCB and the base, L is the maximum length of an orthogonal projection of the pin on the PCB when the pin is contacting the point, and θ is the predetermined angle.

摘要翻译： 用于测试印刷电路板（PCB）的测试装置包括基座和测量装置。 该测量装置包括测试销，并且能够测量PCB的任何所需点，条件是销以与销的大小成比大于预定角度的PCB与背面之间的夹角接触点。 基座和PCB之间的距离满足：H> L tan＆Thetas;其中H是PCB和底座之间的垂直距离，L是当引脚接触时PCB上的销的正交投影的最大长度 点，和＆thetas; 是预定角度。

公开(公告)号：US20120304018A1

公开(公告)日：2012-11-29

申请号：US13278122

申请日：2011-10-20

申请人： JIAN-CHUN PAN ,  HAI-QING ZHOU ,  YI-XIN TU

发明人： JIAN-CHUN PAN ,  HAI-QING ZHOU ,  YI-XIN TU

IPC分类号： G06F11/273

CPC分类号： G06F11/2733 ,  G01R1/0466

摘要： An apparatus for testing a basic input output system (BIOS) chip includes a base and a connector. The base defines a receiving space for housing the BIOS chip. A number of signal pins are formed on sidewalls bounding the receiving space, to electrically connect the BIOS chip. The connector extends from a bottom of the base, and is electrically connected to the signal pins of the base to be connected to a diagnose card to debug the BIOS chip.

摘要翻译： 用于测试基本输入输出系统（BIOS）芯片的装置包括基座和连接器。 基座定义了用于容纳BIOS芯片的接收空间。 多个信号引脚形成在限定接收空间的侧壁上，以电连接BIOS芯片。 连接器从基座的底部延伸，并且电连接到要连接到诊断卡的基座的信号引脚以调试BIOS芯片。

公开(公告)号：US20120268887A1

公开(公告)日：2012-10-25

申请号：US13097103

申请日：2011-04-29

申请人： JIAN-CHUN PAN ,  HAI-QING ZHOU ,  YI-XIN TU

发明人： JIAN-CHUN PAN ,  HAI-QING ZHOU ,  YI-XIN TU

IPC分类号： G06F1/16

CPC分类号： H05K5/0278 ,  H01R13/447 ,  H01R24/62

摘要： A flash drive includes a main body and a casing pivotably installed to a first end of the main body. A universal serial bus (USB) connector extends from a second end of the main body. The casing includes two plates and an end piece perpendicularly connected between ends of the plates. The casing is pivoted toward the USB connector to enclose the USB connector.

摘要翻译： 闪存驱动器包括主体和可枢转地安装到主体的第一端的外壳。 通用串行总线（USB）连接器从主体的第二端延伸。 壳体包括两个板和垂直连接在板的端部之间的端部件。 外壳朝向USB连接器枢转以封闭USB连接器。

公开(公告)号：US20120161799A1

公开(公告)日：2012-06-28

申请号：US13076458

申请日：2011-03-31

申请人： YUN-SHAN XIAO ,  JIAN-CHUN PAN

发明人： YUN-SHAN XIAO ,  JIAN-CHUN PAN

IPC分类号： G01R27/08

CPC分类号： G01R1/06788 ,  G01R27/08

摘要： An exemplary four-wire milliohmmeter includes a main body and two probe assemblies electrically connected with the main body. Each of the probe assemblies includes two plugs detachably inserted into the main body, a contact member, and two wires each electrically connecting one of the plugs to the contact member. The contact portion of each probe assembly has a needlelike free end for contacting an object.

摘要翻译： 示例性的四线毫迹表包括主体和与主体电连接的两个探针组件。 每个探针组件包括可拆卸地插入主体的两个插头，接触构件和两个电线，每个电线将插头中的一个电连接到接触构件。 每个探针组件的接触部分具有用于接触物体的针状自由端。

公开(公告)号：US20090237112A1

公开(公告)日：2009-09-24

申请号：US12205927

申请日：2008-09-08

申请人： CHUNG-CHI HUANG ,  GUANG-DONG YUAN ,  JIAN-CHUN PAN ,  DE-JUN ZENG ,  WEI-MIN ZHANG

发明人： CHUNG-CHI HUANG ,  GUANG-DONG YUAN ,  JIAN-CHUN PAN ,  DE-JUN ZENG ,  WEI-MIN ZHANG

IPC分类号： H03K19/173 ,  H03K19/177

CPC分类号： G06F13/4072

摘要： A programmable logic device (PLD) data transfer cable includes a parallel interface, a programming interface, and a logic control circuit. The parallel interface is used for connecting to PLDs. The logic control circuit includes a first group of transmission channels, a second group of transmission channels, a first group of switches, and a second group of switches. The first and second group of switches control the working status of the first and second group of transmission channels respectively. The electrical connections between pins of the parallel interface and the programming interface when first group of transmission channels are activated are different with those when second group of transmission channels are activated.

摘要翻译： 可编程逻辑器件（PLD）数据传输电缆包括并行接口，编程接口和逻辑控制电路。 并行接口用于连接到PLD。 逻辑控制电路包括第一组传输信道，第二组传输信道，第一组交换机和第二组交换机。 第一组和第二组交换机分别控制第一组和第二组传输信道的工作状态。 当第一组传输通道被激活时，并行接口的引脚和编程接口之间的电连接与第二组传输通道被激活时的电连接不同。

公开(公告)号：US20120131254A1

公开(公告)日：2012-05-24

申请号：US12962591

申请日：2010-12-07

申请人： JIAN-CHUN PAN ,  DE-JUN ZENG ,  CHUNG-CHI HUANG

发明人： JIAN-CHUN PAN ,  DE-JUN ZENG ,  CHUNG-CHI HUANG

IPC分类号： G06F13/36

CPC分类号： G06F3/023 ,  G09G5/006 ,  G09G2370/04 ,  G09G2370/045 ,  G09G2370/047 ,  G09G2370/14

摘要： A switch apparatus includes first to third video graphics array (VGA) interfaces, first to sixth universal serial bus (USB) interfaces, a single-pole double-throw (SPDT) switch, and first to eighteenth electronic switches. The first VGA interface is connected to the second and third VGA interfaces through the electronic switches. The first USB interface is connected the second and third USB interfaces through the electronic switches. The fourth USB interface is connected to the fifth and sixth USB interfaces through the electronic switches. The SPDT switch is used to control the first VGA interface to be selectively connected to the second or third VGA interface, and control the first USB interface to be selectively connected to the second or third USB interface, and control the fourth USB interface to be selectively connected to the fifth or sixth USB interface.

摘要翻译： 开关装置包括第一至第三视频图形阵列（VGA）接口，第一至第六通用串行总线（USB）接口，单刀双掷（SPDT）开关和第一至第十八个电子开关。 第一个VGA接口通过电子开关连接到第二个和第三个VGA接口。 第一个USB接口通过电子开关连接第二个和第三个USB接口。 第四个USB接口通过电子开关连接到第五和第六个USB接口。 SPDT开关用于控制第一VGA接口以选择性地连接到第二或第三VGA接口，并且控制第一USB接口以选择性地连接到第二或第三USB接口，并且控制第四USB接口以选择性地 连接到第五或第六个USB接口。