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    CRITICAL PATH MONITOR HAVING SELECTABLE OPERATING MODES AND SINGLE EDGE DETECTION
    3.
    发明申请
    CRITICAL PATH MONITOR HAVING SELECTABLE OPERATING MODES AND SINGLE EDGE DETECTION 有权
    具有选择性操作模式和单边缘检测的关键路径监视器

    公开(公告)号：US20120043982A1

    公开(公告)日：2012-02-23

    申请号：US12861289

    申请日：2010-08-23

    申请人： Gary D. Carpenter ,  Alan J. Drake ,  Michael S. Floyd ,  Robert M. Senger

    发明人： Gary D. Carpenter ,  Alan J. Drake ,  Michael S. Floyd ,  Robert M. Senger

    IPC分类号： G01R31/3187

    CPC分类号： G01R31/31725

    摘要： A critical path monitor having selectable data output modes provides additional information about critical path delay variation. A pulse is propagated through a synthesized path representing a critical path in a functional logic circuit and a synthesized path delay is measured by a monitoring circuit that detects the arrival of an edge of the pulse at the output of the synthesized delay. The measured delay is provided as a real-time output and a processed result of the measured delay is processed according to a data output mode selected from multiple selectable output modes, thereby providing different information describing the real-time data about critical path delay, such as a range of edge positions corresponding to a variation of the critical path delay.

    摘要翻译： 具有可选数据输出模式的关键路径监视器提供关于关键路径延迟变化的附加信息。 脉冲通过表示功能逻辑电路中的关键路径的合成路径传播，合成路径延迟由检测脉冲边缘在合成延迟的输出处的监控电路测量。 测量的延迟被提供为实时输出，并且根据从多个可选输出模式中选择的数据输出模式来处理测量的延迟的处理结果，从而提供描述关于关键路径延迟的实时数据的不同信息，例如 作为对应于关键路径延迟的变化的边缘位置的范围。

    Critical path monitor having selectable operating modes and single edge detection
    4.
    发明授权
    Critical path monitor having selectable operating modes and single edge detection 有权
    关键路径监视器具有可选择的操作模式和单边缘检测

    公开(公告)号：US08405413B2

    公开(公告)日：2013-03-26

    申请号：US12861289

    申请日：2010-08-23

    申请人： Gary D. Carpenter ,  Alan J. Drake ,  Michael S. Floyd ,  Robert M. Senger

    发明人： Gary D. Carpenter ,  Alan J. Drake ,  Michael S. Floyd ,  Robert M. Senger

    IPC分类号： G01R31/3187

    CPC分类号： G01R31/31725

    摘要： A critical path monitor having selectable data output modes provides additional information about critical path delay variation. A pulse is propagated through a synthesized path representing a critical path in a functional logic circuit and a synthesized path delay is measured by a monitoring circuit that detects the arrival of an edge of the pulse at the output of the synthesized delay. The measured delay is provided as a real-time output and a processed result of the measured delay is processed according to a data output mode selected from multiple selectable output modes, thereby providing different information describing the real-time data about critical path delay, such as a range of edge positions corresponding to a variation of the critical path delay.

    摘要翻译： 具有可选数据输出模式的关键路径监视器提供关于关键路径延迟变化的附加信息。 脉冲通过表示功能逻辑电路中的关键路径的合成路径传播，合成路径延迟由检测脉冲边缘在合成延迟的输出处的监控电路测量。 测量的延迟被提供为实时输出，并且根据从多个可选输出模式中选择的数据输出模式来处理测量的延迟的处理结果，从而提供描述关于关键路径延迟的实时数据的不同信息，例如 作为对应于关键路径延迟的变化的边缘位置的范围。

    PERFORMANCE CONTROL OF FREQUENCY-ADAPTING PROCESSORS BY VOLTAGE DOMAIN ADJUSTMENT
    5.
    发明申请
    PERFORMANCE CONTROL OF FREQUENCY-ADAPTING PROCESSORS BY VOLTAGE DOMAIN ADJUSTMENT 有权
    通过电压调整对频率适配处理器进行性能控制

    公开(公告)号：US20120005513A1

    公开(公告)日：2012-01-05

    申请号：US12827432

    申请日：2010-06-30

    申请人： Bishop C. Brock ,  John B. Carter ,  Alan J. Drake ,  Michael S. Floyd ,  Charles R. Lefurgy ,  Malcolm S. Ware

    发明人： Bishop C. Brock ,  John B. Carter ,  Alan J. Drake ,  Michael S. Floyd ,  Charles R. Lefurgy ,  Malcolm S. Ware

    IPC分类号： G06F1/26 ,  G06F1/04

    CPC分类号： G06F1/3203 ,  G06F1/324 ,  G06F1/3296 ,  Y02D10/126 ,  Y02D10/172

    摘要： A performance control technique for a processing system that includes one or more adaptively-clocked processor cores provides improved performance/power characteristics. An outer feedback loop adjusts the power supply voltage(s) provided to the power supply voltage domain(s) powering the core(s), which may be on a per-core basis or include multiple cores per voltage domain. The outer feedback loop operates to ensure that each core is meeting specified performance, while the cores also include an inner feedback loop that adjusts their processor clock or other performance control mechanism to maximize performance under present operating conditions and within a margin of safety. The performance of each core is measured and compared to a target performance. If the target performance is not met for each core in a voltage domain, the voltage is raised for the voltage domain until all cores meet the target performance.

    摘要翻译： 包括一个或多个自适应时钟的处理器核心的处理系统的性能控制技术提供了改进的性能/功率特性。 外部反馈环路调整提供给供电核心的电源电压域的电源电压（其可以是基于每个核心的或者每个电压域包括多个核心）。 外部反馈环路用于确保每个核心满足指定的性能，而核心还包括一个内部反馈回路，调整其处理器时钟或其他性能控制机制，以最大限度地提高现有操作条件下的性能并在安全范围之内。 测量每个核心的性能并将其与目标性能进行比较。 如果电压域中的每个核心的目标性能不能满足，则电压域的电压将升高，直到所有核心满足目标性能。

    Minimizing power consumption for fixed-frequency processing unit operation
    6.
    发明授权
    Minimizing power consumption for fixed-frequency processing unit operation 有权
    降低固定频率处理单元运行的功耗

    公开(公告)号：US08943341B2

    公开(公告)日：2015-01-27

    申请号：US13443301

    申请日：2012-04-10

    申请人： Malcolm S. Allen-Ware ,  Alan J. Drake ,  Wei Huang ,  Michael S. Floyd ,  Huajun Wen

    发明人： Malcolm S. Allen-Ware ,  Alan J. Drake ,  Wei Huang ,  Michael S. Floyd ,  Huajun Wen

    IPC分类号： G06F1/32

    CPC分类号： G06F1/3296 ,  G06F1/3203 ,  Y02D10/172

    摘要： A mechanism is provided for minimizing power consumption for operation of a fixed-frequency processing unit. A number of timeslots are counted in a time window where throttling is engaged to the fixed-frequency processing unit. The number of timeslots where throttling is engaged is divided by a total number of timeslots within the time window, thereby producing a performance loss (PLOSS) value. A determination is made as to whether determining whether the (PLOSS) value associated with the fixed-frequency processing unit is greater than an allowed performance loss (APLOSS) value. Responsive to the PLOSS value being less than or equal to the APLOSS value, a decrease in voltage supplied to the fixed-frequency processing unit is initiated.

    摘要翻译： 提供了一种用于最小化固定频率处理单元的操作的功耗的机构。 在与固定频率处理单元接合节流的时间窗中计数多个时隙。 将节流作业的时间间隔除以时间窗口内的总时间数，从而产生性能损失（PLOSS）值。 确定确定与固定频率处理单元相关联的（PLOSS）值是否大于允许的性能损失（APLOSS）值。 响应于PLOSS值小于或等于APLOSS值，开始向固定频率处理单元提供的电压的降低。

    Performance control of frequency-adapting processors by voltage domain adjustment
    8.
    发明授权
    Performance control of frequency-adapting processors by voltage domain adjustment 有权
    通过电压域调整对频率适配处理器进行性能控制

    公开(公告)号：US08527801B2

    公开(公告)日：2013-09-03

    申请号：US12827432

    申请日：2010-06-30

    申请人： Bishop C. Brock ,  John B. Carter ,  Alan J. Drake ,  Michael S. Floyd ,  Charles R. Lefurgy ,  Malcolm S. Ware

    发明人： Bishop C. Brock ,  John B. Carter ,  Alan J. Drake ,  Michael S. Floyd ,  Charles R. Lefurgy ,  Malcolm S. Ware

    IPC分类号： G06F1/00

    CPC分类号： G06F1/3203 ,  G06F1/324 ,  G06F1/3296 ,  Y02D10/126 ,  Y02D10/172

    摘要： A performance control technique for a processing system that includes one or more adaptively-clocked processor cores provides improved performance/power characteristics. An outer feedback loop adjusts the power supply voltage(s) provided to the power supply voltage domain(s) powering the core(s), which may be on a per-core basis or include multiple cores per voltage domain. The outer feedback loop operates to ensure that each core is meeting specified performance, while the cores also include an inner feedback loop that adjusts their processor clock or other performance control mechanism to maximize performance under present operating conditions and within a margin of safety. The performance of each core is measured and compared to a target performance. If the target performance is not met for each core in a voltage domain, the voltage is raised for the voltage domain until all cores meet the target performance.

    摘要翻译： 包括一个或多个自适应时钟的处理器核心的处理系统的性能控制技术提供了改进的性能/功率特性。 外部反馈环路调整提供给供电核心的电源电压域的电源电压（其可以是基于每个核心的或者每个电压域包括多个核心）。 外部反馈环路用于确保每个核心满足指定的性能，而核心还包括一个内部反馈回路，调整其处理器时钟或其他性能控制机制，以最大限度地提高现有操作条件下的性能并在安全范围之内。 测量每个核心的性能并将其与目标性能进行比较。 如果电压域中的每个核心的目标性能不能满足，则电压域的电压将升高，直到所有核心满足目标性能。

    Vertical power budgeting and shifting for three-dimensional integration
    9.
    发明授权
    Vertical power budgeting and shifting for three-dimensional integration 有权
    垂直功率预算和三维一体化转移

    公开(公告)号：US08516426B2

    公开(公告)日：2013-08-20

    申请号：US13217429

    申请日：2011-08-25

    申请人： Pradip Bose ,  Gary D. Carpenter ,  Michael S. Floyd ,  Eren Kursun ,  Phillip J. Restle ,  Michael R. Scheuermann

    发明人： Pradip Bose ,  Gary D. Carpenter ,  Michael S. Floyd ,  Eren Kursun ,  Phillip J. Restle ,  Michael R. Scheuermann

    IPC分类号： G06F17/50 ,  G06F9/455 ,  G06F11/22

    CPC分类号： H01L23/50 ,  G06F17/5045 ,  G06F2217/78 ,  H01L25/0657 ,  H01L2224/16145 ,  H01L2225/06513 ,  H01L2225/06544 ,  H01L2225/06565

    摘要： A method is provided for managing power distribution on a three-dimensional chip stack having two or more strata, a plurality of vertical power delivery structures, and multiple stack components. At least two stack components are on different strata. Operating modes are stored that respectively have different power dissipations. A respective effective power budget is determined for each of the at least two stack components based on respective ones of the operating modes targeted therefor, and power characteristics and thermal characteristics of at least some of the stack components inclusive or exclusive of the at least two stack components. The respective ones of the plurality of operating modes targeted for the at least two stack components are selectively accepted or re-allocated based on the respective effective power budget for each of the at least two stack components, power constraints, and thermal constraints. The power constraints include vertical structure electrical constraints.

    摘要翻译： 提供了一种用于管理具有两个或更多个层，多个垂直功率传递结构和多个堆叠组件的三维芯片堆叠上的功率分配的方法。 至少两个堆叠组件位于不同的层。 存储分别具有不同功耗的工作模式。 基于针对其的各个操作模式确定所述至少两个堆叠组件中的每一个的相应的有效功率预算，以及包括或排除所述至少两个堆叠的至少一些堆叠组件的功率特性和热特性 组件。 基于用于至少两个堆叠组件中的每一个，功率约束和热约束的相应的有效功率预算来选择性地接受或重新分配针对至少两个堆叠组件的多个操作模式中的各个操作模式。 功率约束包括垂直结构电气约束。