Encoding assertion and de-assertion of interrupt requests and DMA
requests in a serial bus I/O system
    1.
    发明授权
    Encoding assertion and de-assertion of interrupt requests and DMA requests in a serial bus I/O system 失效
    在串行总线I / O系统中编码断言和解除中断请求和DMA请求

    公开(公告)号:US5634069A

    公开(公告)日:1997-05-27

    申请号:US503795

    申请日:1995-07-18

    摘要: A computing system encodes and emulates requests signals, such as DMA requests or interrupt requests. A first peripheral device is connected to a first request pin of a first input/output (I/O) device. When the first peripheral device asserts a first request signal on the first request pin, a serializer within the first I/O device generates a first packet. The serializer forwards the first packet to a serial out port of the first I/O device. The first packet identifies the type of request and the direction of the edge transition. The serial out port forwards the first packet to a serial in port of a controller device. Upon the serial in port receiving the first packet, an unserializer within the controller device asserts an emulated first request signal, the emulated first request signal being coupled to a first request controller within the controller device. When the first peripheral device de-asserts the first request signal on the first request pin of the first I/O device, the serializer generates a second packet. The second packet identifies the type of request and the direction of the edge transition. The serializer forwards the second packet to the serial out port of the first I/O device. The serial out port of the first I/O device forwards the second packet to the serial in port of the controller device. Upon the serial in port receiving the second packet, the unserializer within the request controller de-asserts the emulated first request signal. When the first peripheral device pulses the first request signal by quickly de-asserting and asserting the first request signal in quick succession, the second packet is sent, but not the first packet.

    摘要翻译: 计算系统对DMA请求或中断请求等请求信号进行编码和仿真。 第一外围设备连接到第一输入/输出(I / O)设备的第一请求引脚。 当第一外围设备在第一请求引脚上断言第一请求信号时,第一I / O设备内的串行器产生第一分组。 串行器将第一个数据包转发到第一个I / O设备的串行输出端口。 第一个数据包标识请求的类型和边沿转换的方向。 串行端口将第一个数据包转发到控制器设备的串行端口。 在串行端口接收第一分组时,控制器设备内的非串行化器断言模拟的第一请求信号,仿真的第一请求信号耦合到控制器设备内的第一请求控制器。 当第一外围设备在第一I / O设备的第一请求引脚上取消断言第一请求信号时,串行器产生第二分组。 第二个分组标识请求的类型和边缘转换的方向。 串行器将第二个数据包转发到第一个I / O设备的串行输出端口。 第一个I / O设备的串行端口将第二个数据包转发到控制器设备的串口。 在串行端口接收第二分组时,请求控制器内的非串行化器取消断言仿真的第一请求信号。 当第一外围设备通过快速地取消断言和断言第一请求信号来脉冲第一请求信号时,发送第二个分组,而不是第一个分组。