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    Encoding assertion and de-assertion of interrupt requests and DMA requests in a serial bus I/O system
    1.
    发明授权
    Encoding assertion and de-assertion of interrupt requests and DMA requests in a serial bus I/O system 失效
    在串行总线I / O系统中编码断言和解除中断请求和DMA请求

    公开(公告)号：US5634069A

    公开(公告)日：1997-05-27

    申请号：US503795

    申请日：1995-07-18

    申请人： Gary D. Hicok ,  David R. Evoy ,  Gary A. Walker ,  Joseph A. Thomsen ,  Lonnie C. Goff ,  Bruce E. Cairns

    发明人： Gary D. Hicok ,  David R. Evoy ,  Gary A. Walker ,  Joseph A. Thomsen ,  Lonnie C. Goff ,  Bruce E. Cairns

    IPC分类号： G06F13/32 ,  G06F13/38 ,  G06F13/42 ,  G06F13/14

    CPC分类号： G06F13/32 ,  G06F13/385 ,  G06F13/423

    摘要： A computing system encodes and emulates requests signals, such as DMA requests or interrupt requests. A first peripheral device is connected to a first request pin of a first input/output (I/O) device. When the first peripheral device asserts a first request signal on the first request pin, a serializer within the first I/O device generates a first packet. The serializer forwards the first packet to a serial out port of the first I/O device. The first packet identifies the type of request and the direction of the edge transition. The serial out port forwards the first packet to a serial in port of a controller device. Upon the serial in port receiving the first packet, an unserializer within the controller device asserts an emulated first request signal, the emulated first request signal being coupled to a first request controller within the controller device. When the first peripheral device de-asserts the first request signal on the first request pin of the first I/O device, the serializer generates a second packet. The second packet identifies the type of request and the direction of the edge transition. The serializer forwards the second packet to the serial out port of the first I/O device. The serial out port of the first I/O device forwards the second packet to the serial in port of the controller device. Upon the serial in port receiving the second packet, the unserializer within the request controller de-asserts the emulated first request signal. When the first peripheral device pulses the first request signal by quickly de-asserting and asserting the first request signal in quick succession, the second packet is sent, but not the first packet.

    摘要翻译： 计算系统对DMA请求或中断请求等请求信号进行编码和仿真。 第一外围设备连接到第一输入/输出（I / O）设备的第一请求引脚。 当第一外围设备在第一请求引脚上断言第一请求信号时，第一I / O设备内的串行器产生第一分组。 串行器将第一个数据包转发到第一个I / O设备的串行输出端口。 第一个数据包标识请求的类型和边沿转换的方向。 串行端口将第一个数据包转发到控制器设备的串行端口。 在串行端口接收第一分组时，控制器设备内的非串行化器断言模拟的第一请求信号，仿真的第一请求信号耦合到控制器设备内的第一请求控制器。 当第一外围设备在第一I / O设备的第一请求引脚上取消断言第一请求信号时，串行器产生第二分组。 第二个分组标识请求的类型和边缘转换的方向。 串行器将第二个数据包转发到第一个I / O设备的串行输出端口。 第一个I / O设备的串行端口将第二个数据包转发到控制器设备的串口。 在串行端口接收第二分组时，请求控制器内的非串行化器取消断言仿真的第一请求信号。 当第一外围设备通过快速地取消断言和断言第一请求信号来脉冲第一请求信号时，发送第二个分组，而不是第一个分组。

    Input/output (I/O) holdoff mechanism for use in a system where I/O device inputs are fed through a latency introducing bus
    2.
    发明授权
    Input/output (I/O) holdoff mechanism for use in a system where I/O device inputs are fed through a latency introducing bus 失效
    输入/输出（I / O）抑制机制，用于通过延迟引入总线馈送I / O设备输入的系统

    公开(公告)号：US5664213A

    公开(公告)日：1997-09-02

    申请号：US504936

    申请日：1995-07-20

    申请人： James C. Steele ,  Gary D. Hicok ,  David R. Evoy ,  Gary A. Walker ,  Joseph A. Thomsen ,  Lonnie C. Goff

    发明人： James C. Steele ,  Gary D. Hicok ,  David R. Evoy ,  Gary A. Walker ,  Joseph A. Thomsen ,  Lonnie C. Goff

    IPC分类号： G06F13/32 ,  G06F13/38 ,  G06F13/42 ,  G06F13/00

    CPC分类号： G06F13/32 ,  G06F13/385 ,  G06F13/423

    摘要： An I/O holdoff mechanism is used to compensate for I/O device inputs being fed through a latency introducing bus. A system includes one or more I/O devices connected through a serial bus to a controller device. Each I/O device includes at least one request pin which is connected to a peripheral device. A serializer in the I/O device responds to a voltage transition occurring on any request pin of the I/O device by forwarding, in a packet over the serial bus, an indicator. The indicator indicates a current voltage on the request pin of the I/O device on which the voltage transition occurred. The controller device includes a deserializer and a bus controller. The deserializer receives the first packet and outputs a signal which indicates a current value for the voltage on the indicated request pin. The deserializer includes a busy output which indicates when the deserializer is busy and when the deserializer is idle. The bus controller responds to a request from a host system for a current value on a first request pin of the I/O device by forwarding to the host system a current value for a voltage on the indicated request pin, as indicated by the deserializer, when the deserializer is not busy. When the deserializer is busy, the bus controller responds to the request from the host system for the current value on the first request pin of the I/O device by waiting for the deserializer to become idle. Upon the deserializer becoming idle, the bus controller forwards to the host system the current value for the voltage on the indicated request pin.

    摘要翻译： 使用I / O缓存机制来补偿通过延迟引入总线馈送的I / O设备输入。 系统包括通过串行总线连接到控制器设备的一个或多个I / O设备。 每个I / O设备包括至少一个连接到外围设备的请求引脚。 I / O设备中的串行器响应I / O设备的任何请求引脚上发生的电压转换，通过串行总线上的数据包转发一个指示器。 该指示灯表示发生电压转换的I / O设备的请求引脚上的当前电压。 控制器设备包括解串器和总线控制器。 解串器接收第一个数据包，并输出指示指示的请求引脚上的电压的当前值的信号。 解串器包括一个忙输出，指示解串器何时正在忙和解串器空闲时。 总线控制器通过向主机系统转发指示的请求引脚上的电压的当前值，如由解串器指示的那样，响应来自主机系统对于I / O设备的第一请求引脚上的当前值的请求， 当解串器不忙时。 当解串器处于忙时，总线控制器通过等待解串器空闲来响应来自主机系统对I / O设备的第一个请求引脚上当前值的请求。 在解串器变为空闲状态时，总线控制器向主机系统转发指定请求引脚上的电压的当前值。

    On chip network
    3.
    发明授权
    On chip network 有权
    片上网络

    公开(公告)号：US07277449B2

    公开(公告)日：2007-10-02

    申请号：US10207298

    申请日：2002-07-29

    申请人： Ned D. Garinger ,  Martin L. Dorr ,  Mark W. Naumann ,  Gary A. Walker

    发明人： Ned D. Garinger ,  Martin L. Dorr ,  Mark W. Naumann ,  Gary A. Walker

    IPC分类号： H04L12/28

    CPC分类号： H04L49/30 ,  H04L49/101 ,  H04L49/102 ,  H04L49/109 ,  H04L49/254

    摘要： An OCN for integrated processing elements including a network with multiple ports and multiple port interfaces. The ports and the port interfaces conform to a consistent port protocol. Each port interface converts information between bus transactions of a corresponding processing element and network packets and exchanges network packets with other port interfaces. Each port includes an arbitration interface and a data interface and the network includes an interconnect and an arbiter. The interconnect includes selectable data paths between the ports for packet datum transfer. A port source interface submits transaction requests and provides packet datums upon receiving an acknowledgement. A port destination interface receives packet datums via available input buffers. Each transaction request includes a transaction size and a destination port address. The arbiter receives transaction requests, arbitrates among transaction requests, provides acknowledgements and controls the interconnect to select data paths between sources and destinations.

    摘要翻译： 用于集成处理元件的OCN，包括具有多个端口和多个端口接口的网络。 端口和端口接口符合一致的端口协议。 每个端口接口在对应处理单元的总线事务和网络数据包之间转换信息，并与其他端口接口交换网络数据包。 每个端口包括仲裁接口和数据接口，并且网络包括互连和仲裁器。 互连包括用于分组数据传输的端口之间的可选数据路径。 端口源接口在接收到确认后提交事务请求并提供数据包基准。 端口目的地接口通过可用的输入缓冲区接收数据包基准。 每个事务请求都包含事务大小和目标端口地址。 仲裁器接收事务请求，在事务请求之间进行仲裁，提供确认并控制互连以选择源和目的地之间的数据路径。

    On chip network with independent logical and physical layers
    6.
    发明授权
    On chip network with independent logical and physical layers 有权
    具有独立逻辑和物理层的片上网络

    公开(公告)号：US07139860B2

    公开(公告)日：2006-11-21

    申请号：US10207588

    申请日：2002-07-29

    申请人： Gary A. Walker ,  Ned D. Garinger ,  Martin L. Dorr ,  Mark W. Naumann

    发明人： Gary A. Walker ,  Ned D. Garinger ,  Martin L. Dorr ,  Mark W. Naumann

    IPC分类号： G06F13/36 ,  G06F5/00

    CPC分类号： G06F15/78

    摘要： An OCN with independent logical and physical layers for enabling communication among integrated processing elements, including ports, bus gaskets and a physical layer interface. Each bus gasket includes a processor element interface and a port interface. Each processor element interface of at least two bus gaskets operates according to a first logical layer protocol. Each port interface operates according to a consistent port interface protocol by sending transaction requests and receiving acknowledgements and by sending and receiving packet datums via the corresponding port. The physical layer interface transfers packets between the ports and includes an arbiter and an interconnect coupled to each port. Additional bus gaskets may be added that operate according to a second logical layer protocol which may or may not be compatible with the first. Any bus gasket may be added that is configured to communicate using multiple logical layer protocols.

    摘要翻译： 具有独立逻辑和物理层的OCN，用于实现集成处理元件之间的通信，包括端口，总线衬垫和物理层接口。 每个总线衬垫包括处理器元件接口和端口接口。 至少两个总线衬垫的每个处理器元件接口根据第一逻辑层协议进行操作。 每个端口接口通过发送事务请求和接收确认以及通过相应端口发送和接收数据包基准，根据一致的端口接口协议进行操作。 物理层接口在端口之间传送数据包，并包括耦合到每个端口的仲裁器和互连。 可以添加额外的总线衬垫，其可以根据第二逻辑层协议操作，第二逻辑层协议可以或可以不与第一逻辑层协议兼容。 可以添加配置为使用多个逻辑层协议进行通信的任何总线衬垫。

    Attachable type beach towel for universal use
    8.
    发明授权
    Attachable type beach towel for universal use 失效
    适用于普遍使用的沙滩巾

    公开(公告)号：US5441789A

    公开(公告)日：1995-08-15

    申请号：US183815

    申请日：1994-01-21

    申请人： Gary A. Walker

    发明人： Gary A. Walker

    IPC分类号： A47C1/14 ,  A47C9/10 ,  B32B3/14 ,  A47C27/00 ,  B32B3/06

    CPC分类号： A47C1/143 ,  A47C31/11 ,  Y10S5/923 ,  Y10T428/23907 ,  Y10T428/24008 ,  Y10T428/24017

    摘要： A attachable type beach towel and chair cover combination for being attached to virtually all types of outdoor seating apparatus, comprising: a elongated substantially rectangularly shaped main body portion of textile fabric beach towel (10) having a pair of side edges and a pair of ends. At the ends are four attaching straps (12) permanently attached at end portions and spaced inwardly from the side edges and four corresponding attaching tabs (14) permanently attached to main body of the beach towel (10) spaced inwardly from the side edges and end portions. The attaching straps (12) and the attaching tabs (14) will be of the hook and loop type fastening system. Two attaching straps (12) and two corresponding attaching tabs (14) will be on opposite sides of the central axis parallel to the side edges and to the central axis parallel to the ends of the beach towel (10), thus making the location of each attaching strap (12) and its corresponding attaching tab (14) generally symmetrical to the others. Included will be four peel and stick attaching tabs (16) which will be of the component of the hook and loop type fastening system that corresponds with the permanently attached attaching straps (12). The four peel and stick attaching tabs (16) will be adhered to the appropriate locations designated by the location of the attaching straps (12) when the attachable type beach towel and chair cover combination is laid out on the type of seating apparatus where there is no frame or strapping to attach to.

    摘要翻译： 一种用于几乎所有类型的户外座椅装置的可附接型沙滩巾和椅子盖组合件，包括：具有一对侧边缘和一对端部的纺织品沙滩巾（10）的细长的大致矩形的主体部分 。 在端部处有四个连接带（12），其永久地附接在端部处并与侧边缘向内间隔开，并且四个相应的附接突舌（14）永久地附接到与侧边缘和端部间隔开的沙滩巾（10）的主体 部分。 附接带（12）和连接片（14）将是钩环式紧固系统。 两个连接带（12）和两个对应的附接突片（14）将在平行于侧边缘的中心轴线的相对侧上并且平行于沙滩巾（10）的端部的中心轴线处， 每个附接带（12）及其对应的附接突片（14）大致对称于其它。 包括将是与永久附接的附接带（12）对应的钩环式紧固系统的部件的四个剥离和粘贴附接突片（16）。 当可附接型沙滩巾和椅子盖组合布置在座椅装置的类型上时，四个剥离和粘贴附接突舌（16）将被粘附到由附接带（12）的位置指定的适当位置 没有框架或绑带附加到。

    On chip network that maximizes interconnect utilization between processing elements
    9.
    发明授权
    On chip network that maximizes interconnect utilization between processing elements 有权
    片上网络，可最大限度地提高处理元件之间的互连利用率

    公开(公告)号：US07200137B2

    公开(公告)日：2007-04-03

    申请号：US10207459

    申请日：2002-07-29

    申请人： Martin L. Dorr ,  Mark W. Naumann ,  Gary A. Walker ,  Ned D. Garinger

    发明人： Martin L. Dorr ,  Mark W. Naumann ,  Gary A. Walker ,  Ned D. Garinger

    IPC分类号： H04L12/28

    CPC分类号： H04L49/254 ,  H04L49/3018

    摘要： A network that maximizes interconnect utilization between integrated processing elements, including ports, an interconnect, port interfaces, and an arbiter. Each port includes arbitration and data interfaces. The interconnect includes selectable data paths between the ports for packet datum transfer. Each port interface includes processing, source and destination interfaces. The source interface submits transaction requests and provides packet datums upon receiving an acknowledgement. The destination interface receives packet datums via a number of available input buffers. Each transaction request includes a transaction size, a packet priority, and a destination port address. The arbiter includes a request queue and a buffer counter for each port and a datum counter for each acknowledged transaction. The arbiter arbitrates among transaction requests based on a selected arbitration scheme, destination buffer availability, data path availability, and priority, and uses the packet datum counters, arbitration latency and data path latency to minimize dead cycles in the interconnect.

    摘要翻译： 最大化集成处理元素之间的互连利用率的网络，包括端口，互连，端口接口和仲裁器。 每个端口包括仲裁和数据接口。 互连包括用于分组数据传输的端口之间的可选数据路径。 每个端口接口包括处理，源和目标接口。 源接口在接收到确认后提交事务请求并提供数据包基准。 目的地接口通过多个可用的输入缓冲区接收数据包基准。 每个事务请求包括事务大小，分组优先级和目标端口地址。 仲裁器包括每个端口的请求队列和缓冲区计数器以及每个确认的事务的基准计数器。 仲裁器根据选定的仲裁方案，目的缓冲区可用性，数据路径可用性和优先级在事务请求之间进行仲裁，并使用分组数据计数器，仲裁延迟和数据路径等待时间来最小化互连中的死循环。

    Scalable on chip network
    10.
    发明授权
    Scalable on chip network 有权
    可扩展的片上网络

    公开(公告)号：US07051150B2

    公开(公告)日：2006-05-23

    申请号：US10207600

    申请日：2002-07-29

    申请人： Mark W. Naumann ,  Gary A. Walker ,  Ned D. Garinger ,  Martin L. Dorr

    发明人： Mark W. Naumann ,  Gary A. Walker ,  Ned D. Garinger ,  Martin L. Dorr

    IPC分类号： G06F13/00

    CPC分类号： G06F15/78

    摘要： A scalable network for supporting an application using processing elements including ports, an interconnect, port interfaces, and an arbiter. Each port conforms to a consistent port interface protocol regardless of number of ports, frequency of operation, maximum datum width or data path concurrency. The interconnect has a scalable maximum datum width and a scalable data path concurrency, and includes selectable data paths between any two ports to enable transfer of datums between the ports. Each port interface formulates packets for transmission and receives packets via the corresponding port and the interconnect, where each packet includes one or more datums. The arbiter controls packet transfer via the interconnect between source and destination ports. The interconnect has a scalable data path concurrency. Pipeline stages may be added to support a selected clock frequency. The OCN may be a component library including bus gasket, interconnect and arbiter components.

    摘要翻译： 可扩展网络，用于使用包括端口，互连，端口接口和仲裁器的处理元件支持应用程序。 每个端口符合一致的端口接口协议，无论端口数量，操作频率，最大基准宽度或数据路径并发。 互连具有可扩展的最大基准宽度和可伸缩的数据路径并发性，并且包括任何两个端口之间的可选数据路径，以实现端口之间的基准传输。 每个端口接口配置数据包进行传输，并通过相应的端口和互连接收数据包，每个数据包包含一个或多个数据。 仲裁器通过源端口和目的端口之间的互连来控制数据包传输。 互连具有可扩展的数据路径并发性。 可以添加管道级以支持选定的时钟频率。 OCN可以是包括总线衬垫，互连和仲裁器组件的组件库。