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公开(公告)号：US06421744B1
公开(公告)日：2002-07-16
申请号：US09426009
申请日：1999-10-25
申请人： Gary R. Morrison , Kristen L. Mason , Frank C. Galloway , Charles E. Nuckolls , Jennifer L. McKeown , Jeffrey M. Polega , Donald L. Tietjen
发明人： Gary R. Morrison , Kristen L. Mason , Frank C. Galloway , Charles E. Nuckolls , Jennifer L. McKeown , Jeffrey M. Polega , Donald L. Tietjen
IPC分类号： G06F928
CPC分类号： G06F13/28
摘要： Direct memory access controller (DMAC) (54) adapted to directly execute C language style FOR tasks assigned by a processor (70), where the FOR task includes a movement of a data element from a first location to a second location in memory. The DMAC includes multiple execution units (EUs) (88, 90, 92), each to perform an arithmetic or logical operation, and a FOR task controller (80, 82, 86) to perform the data movement. The FOR task controller selects the operation to be performed by the EU. In one embodiment, the FOR task is made up of C language type FOR loops, where descriptors identify the control and body of the loop. The descriptors identify the source of operands for an EU, and the source may be changed within a FOR task. A descriptor specifies a function code for an EU and may specify multiple sets of operands for the EU.
摘要翻译： 直接存储器访问控制器（DMAC）（54），其适于直接执行由处理器（70）分配的C语言风格的FOR任务，其中所述FOR任务包括数据元素从存储器中的第一位置移动到第二位置。 DMAC包括执行算术或逻辑运算的多个执行单元（EU）（88,90,92）和用于执行数据移动的FOR任务控制器（80,82,86）。 FOR任务控制器选择由欧盟执行的操作。 在一个实施例中，FOR任务由C语言类型的FOR循环组成，其中描述符标识循环的控制和主体。 描述符标识了EU的操作数来源，并且可以在FOR任务中更改源。 描述符指定EU的功能代码，并且可以指定EU的多组操作数。
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公开(公告)号：US06418489B1
公开(公告)日：2002-07-09
申请号：US09488368
申请日：2000-01-18
申请人： Kristen L. Mason , Gary R. Morrison , Jeffrey M. Polega , Donald L. Tietjen , Frank C. Galloway , Charles Edward Nuckolls , Jennifer L. McKeown , Robert Bradford Cohen
发明人： Kristen L. Mason , Gary R. Morrison , Jeffrey M. Polega , Donald L. Tietjen , Frank C. Galloway , Charles Edward Nuckolls , Jennifer L. McKeown , Robert Bradford Cohen
IPC分类号： G06F1328
CPC分类号： G06F13/28
摘要： Direct memory access controller (DMA) (2) adapted to directly execute C language style FOR tasks, where the FOR task includes a movement of a data element from a first location to a second location in memory, and the movement is controlled by a master DMA engine (MDE) (6). A master DMA engine (MDE) (6) includes a top level state machine (52) to coordinate a context save state machine (54), a parse state machine (56), and a running state machine (58). An loop control descriptor (LCD) queue (74) and a data routing descriptor (DRD) cache store information. The LCD queue allows pipelining of descriptor parsing, while the DRD cache avoids refetching of DRDs on reentry of loops.
摘要翻译： 直接存储器访问控制器（DMA）（2），其适于直接执行C语言风格的FOR任务，其中，所述FOR任务包括数据元素从存储器中的第一位置移动到第二位置，并且移动由主控制器 DMA引擎（MDE）（6）。 主DMA引擎（MDE）（6）包括协调上下文保存状态机（54）的顶级状态机（52），解析状态机（56）和运行状态机（58）。 循环控制描述符（LCD）队列（74）和数据路由描述符（DRD）缓存存储信息。 LCD队列允许流水线描述符解析，而DRD缓存避免在循环重入时重新引导DRD。
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公开(公告)号：US06675235B1
公开(公告)日：2004-01-06
申请号：US09488363
申请日：2000-01-18
申请人： Frank C. Galloway , Kristen L. Mason , Gary R. Morrison , Charles Edward Nuckolls , Jennifer L. McKeown
发明人： Frank C. Galloway , Kristen L. Mason , Gary R. Morrison , Charles Edward Nuckolls , Jennifer L. McKeown
IPC分类号： G06F1314
CPC分类号： G06F13/28
摘要： An execution unit (2) interface protocol allowing flow-through of data, where a function is specified once and the execution unit performs the function for multiple sets of input data. Function execution is pipelined through the execution unit, where an input unit (6) stores information, while a function logic unit (4) processes data and an output unit (8) holds results to be output. The execution unit (2) allows for data rate distortion, in applications such as data compression, where the amount of data received is different from the amount of data generated as output.
摘要翻译： 执行单元（2）允许数据流通的接口协议，其中指定一次功能，并且执行单元执行多组输入数据的功能。 在功能逻辑单元（4）处理数据的同时，输入单元（6）存储信息的执行单元进行功能执行，输出单元（8）保存要输出的结果。 执行单元（2）在诸如数据压缩的应用中允许数据速率失真，其中所接收的数据量不同于作为输出生成的数据量。
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公开(公告)号：US06598192B1
公开(公告)日：2003-07-22
申请号：US09513867
申请日：2000-02-28
IPC分类号： G01R3128
CPC分类号： G01R31/31922 , G01R31/318555
摘要： A programmable clock generator (220), which is part of an integrated circuit (IC) (210), provides clock signals (230) and (232) to various components of the IC. The clock generator includes a PLL (322) and one or more choppers (326, 328) which provide a desired waveform to the IC for testing purposes. When used in conjunction with a tester (212, 312), the IC can be scan tested at-speed using slower and less expensive testing equipment.
摘要翻译： 作为集成电路（IC）（210）的一部分的可编程时钟发生器（220）向IC的各种组件提供时钟信号（230）和（232）。 时钟发生器包括一个PLL（322）和一个或多个斩波器（326,328），它们为了测试目的而向IC提供期望的波形。 当与测试仪（212,312）结合使用时，IC可以使用更慢和更便宜的测试设备进行速度扫描。
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公开(公告)号：US20150379181A1
公开(公告)日：2015-12-31
申请号：US14843659
申请日：2015-09-02
IPC分类号： G06F17/50 , H01L27/02 , H01L27/088 , H01L23/528
CPC分类号： G06F17/5072 , G06F17/5077 , G06F17/5081 , G06F2217/78 , H01L23/528 , H01L27/0207 , H01L27/088 , H01L2924/0002 , H01L2924/00
摘要： This disclosure describes a multi-height routing cell and utilization of the multi-height routing in an integrated circuit to reduce routing congestion in a standard cell design floorplan. The multi-height routing cell includes a bypass connection, or “tunnel,” that routes a signal through a non-routing layer and under an impeding power rail. The multi-height routing cell includes bypass connectors on both sides of the bypass connection that provide connection points for which to connect standard cells on opposite sides of the impeding power rail. As such, the multi-height routing cell provides a route underneath the impeding power rail and, in turn, reducing routing congestion in the standard cell design floorplan.
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公开(公告)号：US09165102B1
公开(公告)日：2015-10-20
申请号：US14246544
申请日：2014-04-07
IPC分类号： G06F17/50
CPC分类号： G06F17/5072 , G06F17/5077 , G06F17/5081 , G06F2217/78 , H01L23/528 , H01L27/0207 , H01L27/088 , H01L2924/0002 , H01L2924/00
摘要： This disclosure describes a multi-height routing cell and utilization of the multi-height routing in an integrated circuit to reduce routing congestion in a standard cell design floorplan. The multi-height routing cell includes a bypass connection, or “tunnel,” that routes a signal through a non-routing layer and under an impeding power rail. The multi-height routing cell includes bypass connectors on both sides of the bypass connection that provide connection points for which to connect standard cells on opposite sides of the impeding power rail. As such, the multi-height routing cell provides a route underneath the impeding power rail and, in turn, reducing routing congestion in the standard cell design floorplan.
摘要翻译： 本公开描述了一种多高度路由单元和集成电路中的多高度路由的利用，以减少标准小区设计平面图中的路由拥塞。 多高度路由单元包括旁路连接或“隧道”，其通过非路由层和阻碍电力轨道路由信号。 多高度路由单元在旁路连接的两侧包括旁路连接器，其提供用于连接阻碍电力轨的相对侧上的标准单元的连接点。 因此，多高度路由单元在阻碍电力轨下面提供路由，从而降低标准小区设计平面图中的路由拥塞。
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公开(公告)号：US20150286768A1
公开(公告)日：2015-10-08
申请号：US14246544
申请日：2014-04-07
IPC分类号： G06F17/50
CPC分类号： G06F17/5072 , G06F17/5077 , G06F17/5081 , G06F2217/78 , H01L23/528 , H01L27/0207 , H01L27/088 , H01L2924/0002 , H01L2924/00
摘要： This disclosure describes a multi-height routing cell and utilization of the multi-height routing in an integrated circuit to reduce routing congestion in a standard cell design floorplan. The multi-height routing cell includes a bypass connection, or “tunnel,” that routes a signal through a non-routing layer and under an impeding power rail. The multi-height routing cell includes bypass connectors on both sides of the bypass connection that provide connection points for which to connect standard cells on opposite sides of the impeding power rail. As such, the multi-height routing cell provides a route underneath the impeding power rail and, in turn, reducing routing congestion in the standard cell design floorplan.
摘要翻译： 本公开描述了一种多高度路由单元和集成电路中的多高度路由的利用，以减少标准小区设计平面图中的路由拥塞。 多高度路由单元包括旁路连接或“隧道”，其通过非路由层和阻碍电力轨道路由信号。 多高度路由单元在旁路连接的两侧包括旁路连接器，其提供用于连接阻碍电力轨的相对侧上的标准单元的连接点。 因此，多高度路由单元在阻碍电力轨下面提供路由，从而降低标准小区设计平面图中的路由拥塞。
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