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公开(公告)号：US08881301B2
公开(公告)日：2014-11-04
申请号：US12898533
申请日：2010-10-05
申请人： Alfred L. Crouch , John C. Potter
发明人： Alfred L. Crouch , John C. Potter
IPC分类号： H04L29/06 , G01R31/3185 , G01R31/317
CPC分类号： G06F21/78 , G01R31/31719 , G01R31/3177 , G01R31/318558 , G01R31/318588 , G06F2221/034
摘要： A network of storage units has a data path which is at least a portion of the network. The network also has a key storage unit and a gateway storage unit. If the key storage unit stores a key value, the key storage unit transmits a key signal to the gateway storage unit. If the gateway storage unit does not store a gateway value or the key signal is not transmitted to the gateway storage unit, the gateway storage unit does not insert a data path segment in the data path. If the gateway storage unit stores a gateway value and the key signal is transmitted to the gateway storage unit, the gateway storage unit inserts the data path segment.
摘要翻译： 存储单元的网络具有作为网络的至少一部分的数据路径。 该网络还具有密钥存储单元和网关存储单元。 如果密钥存储单元存储密钥值，密钥存储单元将密钥信号发送到网关存储单元。 如果网关存储单元不存储网关值，或者密钥信号不发送到网关存储单元，则网关存储单元不在数据路径中插入数据路径段。 如果网关存储单元存储网关值，并且将密钥信号发送到网关存储单元，则网关存储单元插入数据路径段。
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2.发明授权Process for improving design-limited yield by localizing potential faults from production test data 有权通过将生产测试数据中的潜在故障进行定位来提高设计限制产量的过程公开(公告)号：US08615691B2
公开(公告)日：2013-12-24
申请号：US11682314
申请日：2007-03-06
IPC分类号： G01R31/3177 , G01R31/40
CPC分类号： G01R31/318533
摘要： A process for improving design-limited yield by collecting test fail data, converting to electrical faults, and localizing to physical area on semiconductor die. The steps of identifying an area on a wafer containing a fault to enable the analysis of specific defects, accumulating data suitable for yield monitoring analysis based on pattern test failures logged on scan cells in scan chains on automatic test equipment, and translating scan cell and scan chain failure reports to geometric locations of electrical structures on wafers.
摘要翻译： 通过收集测试失败数据，转换为电气故障并将其定位到半导体裸片上的物理区域来提高设计限制产量的过程。 识别包含故障的晶片上的区域以使得能够分析特定缺陷的步骤，基于自动测试设备上的扫描链中记录在扫描单元上的模式测试故障累积适合于产量监测分析的数据，以及翻译扫描单元和扫描 链条故障报告给晶圆上的电气结构的几何位置。
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3.发明授权Method for operating a secure semiconductor IP server to support failure analysis 有权用于操作安全半导体IP服务器以支持故障分析的方法公开(公告)号：US08060851B2
公开(公告)日：2011-11-15
申请号：US11850342
申请日：2007-09-05
IPC分类号： G06F17/50
CPC分类号： G01R31/318541 , G01R31/318552
摘要： A method for operating a secure semiconductor IP access server to support failure analysis. A client presents a test failure and failure type to an automated server which traverses an electronic product design, definition, and test database to report specifically those components and interconnect likely to cause the failure with geometrical information which may be displayed on the client. Other aspects of semiconductor IP are protected by the server by limiting the trace mechanism and renaming components.
摘要翻译： 一种用于操作安全半导体IP访问服务器以支持故障分析的方法。 客户端向自动化服务器呈现测试失败和故障类型，该服务器遍历电子产品设计，定义和测试数据库，以具体报告那些组件和互连可能导致故障与可能在客户端上显示的几何信息。 半导体IP的其他方面由服务器通过限制跟踪机制和重命名组件来保护。
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4.发明申请公开(公告)号：US20090113265A1
公开(公告)日：2009-04-30
申请号：US11931847
申请日：2007-10-31
IPC分类号： G01R31/28
CPC分类号： G01R31/318544 , G01R31/318525 , G01R35/00
摘要： A method for determining that failures in semiconductor test are due to a defect potentially causing a hold time violation in a scan cell in a scan chain, counting the number of potential defects, and, if possible, localizing, and ameliorating hold time defects in a scan chain.
摘要翻译： 用于确定半导体测试中的故障的方法是由于潜在地导致扫描链中的扫描单元中的保持时间违规的缺陷，计数潜在缺陷的数量，以及如果可能的话，定位和改善保持时间缺陷 扫描链。
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5.发明申请PROCESS FOR IMPROVING DESIGN-LIMITED YIELD BY LOCALIZING POTENTIAL FAULTS FROM PRODUCTION TEST DATA 有权通过从生产测试数据中定位潜在缺陷来改进设计有限公司的过程公开(公告)号：US20080091981A1
公开(公告)日：2008-04-17
申请号：US11682314
申请日：2007-03-06
IPC分类号： G06F11/00
CPC分类号： G01R31/318533
摘要： A process for improving design-limited yield by collecting test fail data, converting to electrical faults, and localizing to physical area on semiconductor die. The steps of identifying an area on a wafer containing a fault to enable the analysis of specific defects, accumulating data suitable for yield monitoring analysis based on pattern test failures logged on scan cells in scan chains on automatic test equipment, and translating scan cell and scan chain failure reports to geometric locations of electrical structures on wafers.
摘要翻译： 通过收集测试失败数据，转换为电气故障并将其定位到半导体裸片上的物理区域来提高设计限制产量的过程。 识别包含故障的晶片上的区域以使得能够分析特定缺陷的步骤，基于自动测试设备上的扫描链中记录在扫描单元上的模式测试故障累积适合于产量监测分析的数据，以及翻译扫描单元和扫描 链条故障报告给晶圆上的电气结构的几何位置。
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6.发明授权Method and system for network-on-chip and other integrated circuit architectures 有权网络芯片和其他集成电路架构的方法和系统公开(公告)号：US07348796B2
公开(公告)日：2008-03-25
申请号：US11258661
申请日：2005-10-26
IPC分类号： G06F7/38 , H03K19/173
CPC分类号： H04L45/60 , H04L49/109 , H04L49/555 , H04L49/65
摘要： A method and system is provided for Network-on-Chip (NoC) and other integrated circuit architectures. A configurable fabric circuit (CFC) is interfaced with one or more core circuits and the CFC is responsive to an input signal and capable of reconfiguring the logic circuit in the CFC in accordance with an operational mode determined based on the received input signal to facilitate a core circuit interfaced therewith to carry out an operation consistent with the operational mode.
摘要翻译： 为片上网络（NoC）和其他集成电路架构提供了一种方法和系统。 可配置结构电路（CFC）与一个或多个核心电路接口，并且CFC响应于输入信号并且能够根据基于所接收的输入信号确定的操作模式来重新配置CFC中的逻辑电路，以便于 与其接口的核心电路执行与操作模式一致的操作。
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7.发明授权Method and apparatus for testing a clock stopping/starting function of a low power mode in a data processor 失效用于在数据处理器中测试低功率模式的时钟停止/启动功能的方法和装置
公开(公告)号：US5553236A
公开(公告)日：1996-09-03
申请号：US399113
申请日：1995-03-03
申请人： Juan G. Revilla , Alfred L. Crouch
发明人： Juan G. Revilla , Alfred L. Crouch
IPC分类号： G01R31/317 , G06F1/32 , G06F11/34
CPC分类号： G06F1/324 , G01R31/31701 , G01R31/31721 , G01R31/31724 , G01R31/31727 , G06F1/3203 , G06F2201/88 , Y02B60/1217 , Y02B60/32
摘要： A processor (10) has an internal clock circuit (12), a CPU (14), and a test controller (16). The CPU (14) has a low-power mode of operation and a normal mode of operation. When in low power mode, the internal clock circuit isolates the CPU clock (18) from the internal clock (28) and pulls the internal clock (28) to a stable logic state to ensure that the CPU is not changing state and consuming power. The test controller (16) can be in a low power mode along with the CPU (14) or in a normal mode while the CPU (14) is in the low power mode via the test control signal (26). When the CPU is in low power mode and the controller (16) is in normal mode, the controller (16) tests the operation of the circuit (12) to logically ensure that handling of the clock (18) is proper when entering, maintaining and exiting the low power mode of operation.
摘要翻译： 处理器（10）具有内部时钟电路（12），CPU（14）和测试控制器（16）。 CPU（14）具有低功率操作模式和正常操作模式。 当处于低功耗模式时，内部时钟电路将CPU时钟（18）与内部时钟（28）隔离，并将内部时钟（28）拉至稳定的逻辑状态，以确保CPU不改变状态并消耗电力。 当CPU（14）经由测试控制信号（26）处于低功率模式时，测试控制器（16）可以与CPU（14）一起处于低功率模式或正常模式。 当CPU处于低功率模式并且控制器（16）处于正常模式时，控制器（16）测试电路（12）的操作以逻辑地确保在进入时维护时钟（18）的处理是适当的 并退出低功耗操作模式。
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8.发明申请公开(公告)号：US20170131355A1
公开(公告)日：2017-05-11
申请号：US15347753
申请日：2016-11-09
申请人： James M. Johnson , Alfred L. Crouch
发明人： James M. Johnson , Alfred L. Crouch
IPC分类号： G01R31/317 , G01R31/3177
CPC分类号： G01R31/31719 , G01R31/318588
摘要： A network of storage units has a data path, which is at least a portion of the network. The network also has a dynamic time-varying or cycle-varying code generation unit and a code comparator unit that together make up an unlock signal generation unit; and a gateway storage unit. If the gateway storage unit does not store an unlock signal or the unlock signal generation unit does not generate and transmit an unlock signal, the gateway storage unit does not insert a data path segment in the data path. If the unlock signal generation unit is operated such that it generates an unlock signal, and it transmits that unlock signal to a gateway storage unit, and the gateway storage unit stores the unlock signal value, then the gateway storage unit inserts a data path segment into the data path.
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9.发明申请METHOD FOR OPERATING A SECURE SEMICONDUCTOR IP SERVER TO SUPPORT FAILURE ANALYSIS 有权用于操作安全半导体IP服务器以支持故障分析的方法公开(公告)号：US20100031092A1
公开(公告)日：2010-02-04
申请号：US11850342
申请日：2007-09-05
IPC分类号： G06F11/34
CPC分类号： G01R31/318541 , G01R31/318552
摘要： A method for operating a secure semiconductor IP access server to support failure analysis. A client presents a test failure and failure type to an automated server which traverses an electronic product design, definition, and test database to report specifically those components and interconnect likely to cause the failure with geometrical information which may be displayed on the client. Other aspects of semiconductor IP are protected by the server by limiting the trace mechanism and renaming components.
摘要翻译： 一种用于操作安全半导体IP访问服务器以支持故障分析的方法。 客户端向自动化服务器呈现测试失败和故障类型，该服务器遍历电子产品设计，定义和测试数据库，以具体报告那些组件和互连可能导致故障与可能在客户端上显示的几何信息。 半导体IP的其他方面由服务器通过限制跟踪机制和重命名组件来保护。
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公开(公告)号：US06598192B1
公开(公告)日：2003-07-22
申请号：US09513867
申请日：2000-02-28
IPC分类号： G01R3128
CPC分类号： G01R31/31922 , G01R31/318555
摘要： A programmable clock generator (220), which is part of an integrated circuit (IC) (210), provides clock signals (230) and (232) to various components of the IC. The clock generator includes a PLL (322) and one or more choppers (326, 328) which provide a desired waveform to the IC for testing purposes. When used in conjunction with a tester (212, 312), the IC can be scan tested at-speed using slower and less expensive testing equipment.
摘要翻译： 作为集成电路（IC）（210）的一部分的可编程时钟发生器（220）向IC的各种组件提供时钟信号（230）和（232）。 时钟发生器包括一个PLL（322）和一个或多个斩波器（326,328），它们为了测试目的而向IC提供期望的波形。 当与测试仪（212,312）结合使用时，IC可以使用更慢和更便宜的测试设备进行速度扫描。
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