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公开(公告)号：US5744984A
公开(公告)日：1998-04-28
申请号：US748641
申请日：1996-11-13
CPC分类号： H02J7/0068 , G05F1/613 , G08B3/1066 , H03K17/14 , H03K17/60
摘要： A driver circuit (100) is utilized to drive a high current load (116) in an electronic device powered by a battery (118) having a terminal voltage which varies in relation to a level of energy being consumed. The driver circuit (100) includes a differential amplifier (110) which is responsive to a predetermined reference voltage and to the terminal voltage for generating a drive control signal which proportionally reduces a current supplied to the high current load (114) when the terminal voltage is substantially equal to and lower than the predetermined reference voltage. A slope control element (112) is coupled to the differential amplifier (110) to control a rate at which the drive control signal reduces proportionally the current supplied to the high current load (116). A load control element (114), coupled to the differential amplifier (100), provides the supply of current to the high current load (116).
摘要翻译： 驱动器电路（100）用于驱动由电池（118）供电的电子设备中的高电流负载（116），该电池具有相对于被消耗的能量水平而变化的端电压。 驱动器电路（100）包括响应于预定参考电压的差分放大器（110）和用于产生驱动控制信号的端子电压，所述驱动控制信号当端电压（114）被成比例地减小提供给高电流负载（114）的电流 基本上等于和低于预定参考电压。 斜率控制元件（112）耦合到差分放大器（110）以控制驱动控制信号成比例地减小提供给高电流负载（116）的电流的速率。 耦合到差分放大器（100）的负载控制元件（114）向高电流负载（116）提供电流供应。
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公开(公告)号：US5111486A
公开(公告)日：1992-05-05
申请号：US324277
申请日：1989-03-15
CPC分类号： H04W88/022 , H03L7/0992 , H04L7/0331 , H04L7/046 , H04L7/10
摘要： A paging receiver capable of bit synchronizing to one of two data rates. The receiver has a digital phase locked loop integrated onto a single integrated circuit clocked by a single frequency crystal. The paging receiver receives and synchronizes to a POCSAG signal which may be transmitted at either 512 bits per second or 1200 bits per second. The digital phase locked loop bit synchronizes to either data rate using a single crystal frequency of 76.8 kHz. The data rate is selected by a bit in the code paging receiver's code plug. The digital phase locked loop is constructed to have a substantially constant frequency to bandwidth ratio at both data rates.
摘要翻译： 能够与两个数据速率之一进行位同步的寻呼机。 接收器具有集成到由单个频率晶体驱动的单个集成电路上的数字锁相环。 寻呼接收机接收并同步到可以以每秒512位或每秒1200位发送的POCSAG信号。 使用76.8 kHz的单晶体频率，数字锁相环位与数据速率同步。 数据速率由代码寻呼接收机的代码插头中的一位选择。 数字锁相环被构造为在两个数据速率下具有基本恒定的频率与带宽比。
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公开(公告)号：US5399956A
公开(公告)日：1995-03-21
申请号：US829833
申请日：1992-02-03
CPC分类号： H02J9/061 , Y10T307/625
摘要： In a device having a primary battery 10, a first voltage multiplier 20 is used to power digital electrical circuits 40 from the primary battery, and a second voltage multiplier 100-136 is used to recharge a backup battery 50 from the primary battery. The backup battery is charged to a voltage greater than the voltage generated by the first voltage multiplier. Methods of controlling the second voltage multiplier reduce its interference in measurement of device parameters, and reduce the power consumed from the primary battery.
摘要翻译： 在具有一次电池10的装置中，第一电压倍增器20用于为来自初级电池的数字电路40供电，并且第二电压倍增器100-136用于从一次电池对备用电池50充电。 备用电池被充电到大于由第一电压倍增器产生的电压的电压。 控制第二电压倍增器的方法降低其对器件参数测量的干扰，并减少从一次电池消耗的功率。
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