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    Microprocessor system bus protocol providing a fully pipelined input/output DMA write mechanism
    3.
    发明授权
    Microprocessor system bus protocol providing a fully pipelined input/output DMA write mechanism 失效
    微处理器系统总线协议提供完全流水线的输入/输出DMA写入机制

    公开(公告)号：US06782456B2

    公开(公告)日：2004-08-24

    申请号：US09915432

    申请日：2001-07-26

    申请人： Ravi Kumar Arimilli ,  George William Daly, Jr. ,  Paul K. Umbarger

    发明人： Ravi Kumar Arimilli ,  George William Daly, Jr. ,  Paul K. Umbarger

    IPC分类号： G06F1200

    CPC分类号： G06F12/0835 ,  G06F13/28

    摘要： A method and data processing system that supports pipelining of Input/Output (I/O) DMA Write transactions. An I/O processor's operational protocol is provided with a pair of instructions/commands that are utilized to complete a DMA Write operation. The instructions are DMA_Write_No_Data and DMA_Write_With_Data. DMA_Write_No_Data is an address-only operation on the system bus that is utilized to acquire ownership of a cache line that is to be written. The ownership of the cache line is marked by a weak DMA state, which indicates that the cache line is being held for writing to the memory, but that the cache line cannot yet force a retry of snooped operations. When each preceding DMA Write operation has completed or each corresponding DMA_Write_No_Data operation has been placed in a DMA Exclusive state, then the weak DMA state is changed to a DMA Exclusive state, which forces a retry of snooped operations until the write transaction to memory is completed. In this way, DMA Writes that are provided sequentially may be issued in a parallel manner on the system bus and their corresponding DMA_Write_No_Data operations may be completed in any order, but cannot be made DMA Exclusive unless the above conditions are satisfied. Further, once a DMA Exclusive state is acquired, a DMA_Write_With_Data may be issued for each of the sequential DMA Write operations in the DMA Exclusive state. The DMA_Write_With_Data may then be completed out-of-order with respect to each other. However, the system processor is sent the completion messages in the sequential order of the DMA Write operations, thus adhering to the processor requirements for ordered operations while providing fully-pipelined (parallel) execution of the DMA transactions.

    摘要翻译： 支持输入/输出（I / O）DMA写入事务流水线的方法和数据处理系统。 I / O处理器的操作协议提供有一对用于完成DMA写操作的指令/命令。 指令是DMA_Write_No_Data和DMA_Write_With_Data。 DMA_Write_No_Data是用于获取要写入的高速缓存行的所有权的系统总线上的仅地址操作。 高速缓存行的所有权标记为弱DMA状态，这表示高速缓存行被保留用于写入内存，但高速缓存行不能强制重试侦听操作。 当前一个DMA写操作完成或每个相应的DMA_Write_No_Data操作已经被置于DMA独占状态时，则弱DMA状态被改变为DMA独占状态，这迫使重复执行窥探操作，直到对存储器的写事务完成 。 以这种方式，顺序提供的DMA写入可以以并行方式发布在系统总线上，并且它们相应的DMA_Write_No_Data操作可以以任何顺序完成，但是除非满足上述条件，否则不能进行DMA独占。 此外，一旦获取DMA独占状态，可以在DMA独占状态中为每个顺序DMA写操作发出DMA_Write_With_Data。 然后可以相对于彼此完成无序的DMA_Write_With_Data。 然而，系统处理器按照DMA写操作的顺序发送完成消息，因此在提供完全流水线（并行）DMA事务的执行的同时，遵循处理器对有序操作的要求。

    Method to preserve ordering of read and write operations in a DMA system by delaying read access
    4.
    发明授权
    Method to preserve ordering of read and write operations in a DMA system by delaying read access 有权
    通过延迟读访问来保持DMA系统中读写操作顺序的方法

    公开(公告)号：US07243194B2

    公开(公告)日：2007-07-10

    申请号：US11054403

    申请日：2005-02-09

    申请人： George William Daly, Jr. ,  James Stephen Fields, Jr. ,  Paul K. Umbarger ,  Kenneth Lee Wright

    发明人： George William Daly, Jr. ,  James Stephen Fields, Jr. ,  Paul K. Umbarger ,  Kenneth Lee Wright

    IPC分类号： G06F12/00

    CPC分类号： G06F13/28 ,  G06F12/0815 ,  G06F12/0897

    摘要： A method, system and computer program product for handling write requests in a data processing system is disclosed. The method comprises receiving on an interconnect bus a first write request targeted to a first address and receiving on the interconnect bus a subsequent second write request targeted to a subsequent second address. The subsequent second write request is completed prior to completing the first write request, and, responsive to receiving a read request targeting the second address before the first write request has completed, data associated with the second address of the second write request is supplied only after the first write request completes.

    摘要翻译： 公开了一种用于在数据处理系统中处理写入请求的方法，系统和计算机程序产品。 该方法包括在互连总线上接收针对第一地址的第一写入请求，并且在互连总线上接收针对随后的第二地址的后续的第二写入请求。 随后的第二写请求在完成第一写请求之前完成，并且响应于在第一写请求完成之前接收到针对第二地址的读请求，与第二写请求的第二地址相关联的数据仅在 第一个写请求完成。

    DMA exclusive cache state providing a fully pipelined input/output DMA write mechanism
    5.
    发明授权
    DMA exclusive cache state providing a fully pipelined input/output DMA write mechanism 失效
    DMA独占缓存状态提供完全流水线的输入/输出DMA写入机制

    公开(公告)号：US06785776B2

    公开(公告)日：2004-08-31

    申请号：US09915669

    申请日：2001-07-26

    申请人： Ravi Kumar Arimilli ,  George William Daly, Jr. ,  Paul K. Umbarger

    发明人： Ravi Kumar Arimilli ,  George William Daly, Jr. ,  Paul K. Umbarger

    IPC分类号： G06F1200

    CPC分类号： G06F13/28 ,  G06F12/0835

    摘要： A data processing system that provides a DMA Exclusive state that enables pipelining of Input/Output (I/O) DMA Write transactions. The data processing system includes a system processor, a system bus, a memory, a plurality of I/O components and an I/O processor. The data processing system further comprises operational protocol providing a pair of instructions/commands that are utilized to complete a DMA Write operation. The pair of instructions is DMA_Write_No_Data and DMA_Write With_Data. DMA_Write_No_Data is an address-only operation on the system bus that is utilized to acquire “DMA ownership” of a cache line that is to be written. The initial ownership of the cache line is marked by a weak DMA state (D1), which indicates that the cache line is being held for writing to the memory, but that the cache line cannot yet force a retry of snooped operations. When each preceding DMA Write operation has completed or each corresponding DMA_Write_No_Data operation has been placed in a DMA Exclusive (D2) state, then the next cache line in a weak DMA state transitions to a DMA Exclusive (D2) state, which forces a retry of snooped operations until the DMA_Write_With_Data transaction to memory is completed. Accordingly, DMA_Write_No_Data operations that are provided sequentially may be completed in a parallel manner on the system bus although the corresponding DMA_Write_With_Data is held until a DMA Exclusive state attaches to the cache line. Also, the DMA_Write_With_Data may be completed out of order and once the write of the cache line is completed, the coherency state transitions from the DMA Exclusive state to the MESI Exclusive (E) state or the MESI Invalidate (I) state depending on processor operating characteristics.

    摘要翻译： 一种数据处理系统，提供支持输入/输出（I / O）DMA写入事务流水线的DMA独占状态。 数据处理系统包括系统处理器，系统总线，存储器，多个I / O组件和I / O处理器。 数据处理系统还包括提供用于完成DMA写入操作的一对指令/命令的操作协议。 该对指令是DMA_Write_No_Data和DMA_Write With_Data。 DMA_Write_No_Data是用于获取要写入的高速缓存行的“DMA所有权”的系统总线上的仅地址操作。 高速缓存行的初始所有权由弱DMA状态（D1）标记，表示高速缓存行被保留用于写入存储器，但缓存行不能强制重试监视操作。 当每个先前的DMA写操作完成或每个对应的DMA_Write_No_Data操作已经被置于DMA独占（D2）状态时，则处于弱DMA状态的下一个高速缓存行转换到DMA独占（D2）状态，这迫使重新执行 窥探操作，直到DMA_Write_With_Data事务到内存完成。 因此，顺序提供的DMA_Write_No_Data操作可以以并行方式在系统总线上完成，尽管相应的DMA_Write_With_Data被保持，直到DMA独占状态连接到高速缓存行。 此外，DMA_Write_With_Data可能无序完成，并且一旦高速缓存行的写入完成，则一致性状态根据处理器操作从DMA排除状态转换到MESI独占（E）状态或MESI无效（I）状态 特点