公开(公告)号：US06463554B1

公开(公告)日：2002-10-08

申请号：US09156179

申请日：1998-09-17

申请人： Gerald A Budelman ,  William A. Hobbs ,  Stephen J. Peters ,  Tsvika Kurts ,  Nitin V. Sarangdhar ,  Kenneth B. Oliver

发明人： Gerald A Budelman ,  William A. Hobbs ,  Stephen J. Peters ,  Tsvika Kurts ,  Nitin V. Sarangdhar ,  Kenneth B. Oliver

IPC分类号： G06F1100

CPC分类号： G06F11/349 ,  G06F11/004 ,  G06F11/221 ,  G06F11/25 ,  G06F2201/88 ,  H04L41/0631 ,  H04L43/0811 ,  H04L43/12

摘要： An apparatus including a protocol watcher adapted for use with a bus, a state machine adapted to detect known bug signatures on the bus, and a perturber adapted to intervene on the bus to prevent occurrence of bugs having those signatures. A system utilizing such includes a bus, a first agent coupled to the bus, a second agent coupled to the bus for communicating to the first agent according to a bus protocol, and the bus patcher coupled to the bus for monitoring a communication from the second agent to the first agent to identify an event which would cause an error in the apparatus, and for modifying the communication such that the event is avoided. Any of the protocol watcher, state machine, and/or perturber may be programmable.

摘要翻译： 一种包括适于与总线一起使用的协议观察器的装置，适用于检测总线上的已知错误签名的状态机，以及适用于在总线上干预以防止发生具有这些签名的错误的扰码器。 一种使用这种系统的系统包括总线，耦合到总线的第一代理，耦合到总线的第二代理，用于根据总线协议与第一代理进行通信，并且总线修补器耦合到总线，用于监视来自第二个 代理到第一代理以识别将导致设备中的错误的事件，以及用于修改通信，使得避免事件。 任何协议监视器，状态机和/或监听器都可以是可编程的。

公开(公告)号：US5819027A

公开(公告)日：1998-10-06

申请号：US607943

申请日：1996-02-28

申请人： Gerald A. Budelman ,  William A. Hobbs ,  Stephen J. Peters ,  Tsvika Kurts ,  Nitin V. Sarangdhar ,  Kenneth B. Oliver

发明人： Gerald A. Budelman ,  William A. Hobbs ,  Stephen J. Peters ,  Tsvika Kurts ,  Nitin V. Sarangdhar ,  Kenneth B. Oliver

IPC分类号： G06F11/00 ,  G06F11/25 ,  G06F11/267 ,  G06F11/34 ,  H04L12/24

CPC分类号： G06F11/349 ,  G06F11/004 ,  H04L41/0631 ,  H04L43/0811 ,  H04L43/12 ,  G06F11/221 ,  G06F11/25 ,  G06F2201/88

摘要： An apparatus including a protocol watcher adapted for use with a bus, a state machine adapted to detect known bug signatures on the bus, and a perturber adapted to intervene on the bus to prevent occurrence of bugs having those signatures. A system utilizing such includes a bus, a first agent coupled to the bus, a second agent coupled to the bus for communicating to the first agent according to a bus protocol, and the bus patcher coupled to the bus for monitoring a communication from the second agent to the first agent to identify an event which would cause an error in the apparatus, and for modifying the communication such that the event is avoided. Any of the protocol watcher, state machine, and/or perturber may be programmable.

公开(公告)号：US20140281763A1

公开(公告)日：2014-09-18

申请号：US13842320

申请日：2013-03-15

申请人： Adee O. Ran ,  Amir Mezer ,  Ophir Gazinski ,  Sanjay R. Ravi ,  David G. Ellis ,  Stephen J. Peters ,  Jeffrey M. Shuey

发明人： Adee O. Ran ,  Amir Mezer ,  Ophir Gazinski ,  Sanjay R. Ravi ,  David G. Ellis ,  Stephen J. Peters ,  Jeffrey M. Shuey

IPC分类号： G06F11/07

CPC分类号： H04L1/203

摘要： A sample voltage is received from a device at a first slicer element and a second slicer element. A decision by the first slicer element based on the sample voltage is identified and compared with a decision of the second slicer element based on the sample voltage. The decision of the second slicer element is to be generated from a comparison of the sample voltage with a reference voltage for the second slicer element. Comparing the decisions can be the basis of a soft error ration determined for a device.

摘要翻译： 从第一限幅元件和第二限幅元件的装置接收采样电压。 基于样本电压确定第一限幅元件的判定，并根据采样电压与第二限幅元件的判定进行比较。 第二限幅元件的决定是从采样电压与第二限幅元件的参考电压的比较产生的。 比较决策可以是为设备确定的软错误比例的基础。

公开(公告)号：US5513338A

公开(公告)日：1996-04-30

申请号：US30801

申请日：1993-03-12

申请人： James W. Alexander ,  Terri A. Danowski ,  Stephen J. Peters ,  Ronald J. Whitsel

发明人： James W. Alexander ,  Terri A. Danowski ,  Stephen J. Peters ,  Ronald J. Whitsel

IPC分类号： G06F11/36 ,  G06F11/00 ,  G06F13/00

CPC分类号： G06F11/364 ,  G06F11/3632

摘要： An in-circuit emulator trace bus clocking mechanism. A synchronization clock associated with the trace bus is provided. Arrival of a first event on a microprocessor bus to be traced is signified by a transition of a control line. A start of cycle event is detected. A start of cycle signal is generated with respect to the start of cycle event. A two stage pipeline having stage 1 storage elements and stage 2 storage elements are connected to receive data from the microprocessor bus. The start of cycle signal is used to sample data from the microprocessor bus into the stage 1 storage elements. An end of cycle event is detected. An end of cycle signal is generated with reference to the end of cycle event. The end of cycle signal is used to sample data from the stage 1 storage elements into the stage 2 storage elements. The end of cycle signal is also used to sample data appearing on the microprocessor bus at the end of the cycle into the stage 2 storage elements. The synchronization clock is combined with the end of cycle signal to generate a trace bus valid signal.

摘要翻译： 在线仿真器跟踪总线时钟机制。 提供与跟踪总线相关联的同步时钟。 要跟踪的微处理器总线上的第一个事件的到达是通过控制线的转换来表示的。 检测到循环事件的开始。 相对于循环事件的开始产生循环信号的开始。 连接具有第一级存储元件和第二级存储元件的两级流水线，以从微处理器总线接收数据。 循环信号的启动用于将数据从微处理器总线采样到第1级存储单元中。 检测到循环事件的结束。 参考周期事件的结束生成周期信号的结束。 周期信号的结束被用于从第1级存储元件将数据采样到第2级存储元件中。 循环信号的结束也用于将循环结束时出现在微处理器总线上的数据采样到第2级存储单元中。 同步时钟与周期信号的结束相结合，生成跟踪总线有效信号。