公开(公告)号：US06388884B1

公开(公告)日：2002-05-14

申请号：US09583433

申请日：2000-05-31

申请人： Gerry A. Greco ,  Salvatore R. Giammanco ,  Charles A. Eley ,  Scot W. Salzman

发明人： Gerry A. Greco ,  Salvatore R. Giammanco ,  Charles A. Eley ,  Scot W. Salzman

IPC分类号： H05K714

CPC分类号： H05K7/1409 ,  H01H9/20

摘要： An apparatus and method for activating a switch with a circuit board ejector includes a circuit board and a switch assembly including the switch for transitioning the circuit board from a first mode to a second mode and vice versa. The switch assembly is attached to the circuit board, and the circuit board ejector is rotatably attached to the circuit board to allow the circuit board ejector to be positioned in an unlatched position and a latched position. The circuit board ejector includes a hook portion and a bracket arm wherein the bracket arm of the circuit board ejector activates the switch assembly and causes the circuit board to transition from the first mode to the second mode and vice versa.

摘要翻译： 用于利用电路板喷射器激活开关的装置和方法包括电路板和开关组件，开关组件包括用于将电路板从第一模式转换到第二模式的开关，反之亦然。 开关组件附接到电路板，并且电路板顶出器可旋转地附接到电路板，以允许电路板顶板定位在解锁位置和锁定位置。 电路板顶出器包括钩部和支架臂，其中电路板顶出器的支架臂启动开关组件，并使电路板从第一模式转换到第二模式，反之亦然。

公开(公告)号：US09886282B2

公开(公告)日：2018-02-06

申请号：US13280964

申请日：2011-10-25

申请人： Stephen A. Canterbury ,  Vernon W. Hamlin ,  Scot W. Salzman ,  Jorge L. Shimabukuro ,  Craig J. Sylla

发明人： Stephen A. Canterbury ,  Vernon W. Hamlin ,  Scot W. Salzman ,  Jorge L. Shimabukuro ,  Craig J. Sylla

IPC分类号： G06F9/44 ,  G06F21/57 ,  G06F21/64 ,  G07F17/32

CPC分类号： G06F9/4401 ,  G06F21/572 ,  G06F21/575 ,  G06F21/64 ,  G07F17/3227

摘要： In some embodiments, a wagering game machine includes: a carrier board comprising a first network port and a second network port, the first network port having a first network address and the second network port having a second network address; a processor located on the carrier board; a first nonvolatile memory located on the carrier board and communicatively coupled to the first network port, the first nonvolatile memory configured to store the first network address; and a second nonvolatile memory located on the carrier board, wherein the second nonvolatile memory is configured to store Basic Input and Output System (BIOS) code that includes a system BIOS code and an application BIOS code, wherein the BIOS code is hardware write-protected, wherein the processor is configured to derive the second network address from the first network address during execution of boot-up operations of the apparatus.

公开(公告)号：US5438614A

公开(公告)日：1995-08-01

申请号：US249169

申请日：1994-05-25

申请人： Christopher J. Rozman ,  Scot W. Salzman

发明人： Christopher J. Rozman ,  Scot W. Salzman

IPC分类号： H04L12/24 ,  H04M11/06 ,  H04M11/00

CPC分类号： H04L41/0213 ,  H04L41/24 ,  H04M11/06

摘要： Apparatus and method for managing transmission of digital data between a digital telephone line and a computer network. First and second modems, a telephone control circuit and a network control circuit respond to management instruction signals to execute predetermined management objectives and generate management response signals representing one or more conditions of the first and second modems, telephone control circuit and network control circuit. In response to a single packet of management signals from the network, a management circuit generates the management instruction signals and independently addresses them to one or more of the first and second modems, telephone control circuit and network control circuit.

摘要翻译： 用于管理数字电话线和计算机网络之间的数字数据传输的装置和方法。 第一和第二调制解调器，电话控制电路和网络控制电路响应于管理指令信号以执行预定的管理目标，并产生表示第一和第二调制解调器，电话控制电路和网络控制电路的一个或多个条件的管理响应信号。 响应于来自网络的单个管理信号包，管理电路产生管理指令信号并且独立地将它们解码到第一和第二调制解调器，电话控制电路和网络控制电路中的一个或多个。

公开(公告)号：US20120208619A1

公开(公告)日：2012-08-16

申请号：US13280964

申请日：2011-10-25

申请人： Stephen A. Canterbury ,  Vernon W. Hamlin ,  Scot W. Salzman ,  Jorge L. Shimabukuro ,  Craig J. Sylla

发明人： Stephen A. Canterbury ,  Vernon W. Hamlin ,  Scot W. Salzman ,  Jorge L. Shimabukuro ,  Craig J. Sylla

IPC分类号： A63F9/24 ,  G06F15/177

CPC分类号： G06F9/4401 ,  G06F21/572 ,  G06F21/575 ,  G06F21/64 ,  G07F17/3227

摘要： In some embodiments, a wagering game machine includes: a carrier board comprising a first network port and a second network port, the first network port having a first network address and the second network port having a second network address; a processor located on the carrier board; a first nonvolatile memory located on the carrier board and communicatively coupled to the first network port, the first nonvolatile memory configured to store the first network address; and a second nonvolatile memory located on the carrier board, wherein the second nonvolatile memory is configured to store Basic Input and Output System (BIOS) code that includes a system BIOS code and an application BIOS code, wherein the BIOS code is hardware write-protected, wherein the processor is configured to derive the second network address from the first network address during execution of boot-up operations of the apparatus.

摘要翻译： 在一些实施例中，投注游戏机包括：承载板，包括第一网络端口和第二网络端口，所述第一网络端口具有第一网络地址，所述第二网络端口具有第二网络地址; 位于载板上的处理器; 第一非易失性存储器，位于所述载板上并且通信地耦合到所述第一网络端口，所述第一非易失性存储器被配置为存储所述第一网络地址; 以及位于所述载板上的第二非易失性存储器，其中所述第二非易失性存储器被配置为存储包括系统BIOS代码和应用BIOS代码的基本输入和输出系统（BIOS）代码，其中所述BIOS代码是硬件写保护的 ，其中所述处理器被配置为在所述装置的引导操作的执行期间从所述第一网络地址导出所述第二网络地址。

公开(公告)号：US20120208633A1

公开(公告)日：2012-08-16

申请号：US13280930

申请日：2011-10-25

申请人： Scot W. Salzman

发明人： Scot W. Salzman

IPC分类号： A63F9/24

CPC分类号： G06F9/4401 ,  G06F21/572 ,  G06F21/575 ,  G06F21/64 ,  G07F17/3227

摘要： Embodiments include a method for configuring basic input/output system (BIOS) of a wagering game machine. The method can include: initializing a processor and chipset residing on an embedded computer module residing in the wagering game machine, wherein the BIOS resides on a carrier board connected to the embedded computer module; identifying, under control of code in the BIOS, the embedded computer module as a particular one of a plurality of embedded computer modules, wherein the BIOS includes code for configuring each of the plurality of embedded computer modules; initializing, using code of the BIOS configured for the particular one of the plurality of embedded computer modules, input/output devices connected to the carrier board and embedded computer module; launching, under control of the BIOS, an operating system in the wagering game machine; presenting a wagering game on the wagering game machine, wherein the presenting utilizes information received from the input/output devices.

摘要翻译： 实施例包括用于配置投注游戏机的基本输入/输出系统（BIOS）的方法。 该方法可以包括：初始化驻留在投注游戏机中的嵌入式计算机模块上的处理器和芯片组，其中BIOS驻留在连接到嵌入式计算机模块的载板上; 在所述BIOS中的代码的控制下，将所述嵌入式计算机模块识别为多个嵌入式计算机模块中的特定一个，其中所述BIOS包括用于配置所述多个嵌入式计算机模块中的每一个的代码; 初始化使用为所述多个嵌入式计算机模块中的特定一个配置的BIOS的代码，连接到所述载板和嵌入式计算机模块的输入/输出设备; 在BIOS的控制下启动投注游戏机中的操作系统; 在投注游戏机上呈现投注游戏，其中呈现利用从输入/输出设备接收的信息。

公开(公告)号：US06230181B1

公开(公告)日：2001-05-08

申请号：US08963402

申请日：1997-11-03

申请人： Craig G. Mitchell ,  Michael P. Dempsey ,  Christian A. D'Souza ,  Chandra S. Pandey ,  Scot W. Salzman

发明人： Craig G. Mitchell ,  Michael P. Dempsey ,  Christian A. D'Souza ,  Chandra S. Pandey ,  Scot W. Salzman

IPC分类号： G06F900

CPC分类号： G06F9/442 ,  G06F11/1441

摘要： A system for shutting down and resetting an embedded system having a general purpose computing platform. A shutdown management driver generates a management reset according to a predetermined set of shutdown conditions. The shutdown and reset manager receive the management reset signal and initiate a shutdown of the operating system. When the operating system has shutdown, the second receipt of the management reset signal initiates a hardware reset.

摘要翻译： 一种用于关闭和重置具有通用计算平台的嵌入式系统的系统。 关闭管理驱动程序根据预定的一组停机条件产生管理复位。 关闭和复位管理器接收管理复位信号并启动操作系统的关闭。 当操作系统关闭时，管理复位信号的第二次接收启动硬件复位。

公开(公告)号：US5438536A

公开(公告)日：1995-08-01

申请号：US223103

申请日：1994-04-05

申请人： Scot W. Salzman

发明人： Scot W. Salzman

IPC分类号： G11C5/14 ,  G11C8/12 ,  G11C13/00

CPC分类号： G11C8/12 ,  G11C5/14

摘要： A module incorporating flash memory chips. An interface enables power down of the chips in response to a power down signal and provides an interrupt signal indicating when all of the ready lines from the memory chips are in a ready state, thereby reducing the need for polling the status registers in the chips.

摘要翻译： 包含闪存芯片的模块。 一个接口可以响应于断电信号使芯片掉电，并提供指示何时来自存储器芯片的所有就绪线路处于就绪状态的中断信号，从而减少轮询芯片中的状态寄存器的需要。

公开(公告)号：US09122492B2

公开(公告)日：2015-09-01

申请号：US13280930

申请日：2011-10-25

申请人： Scot W. Salzman

发明人： Scot W. Salzman

IPC分类号： G06F9/44 ,  G06F21/57 ,  G06F21/64

CPC分类号： G06F9/4401 ,  G06F21/572 ,  G06F21/575 ,  G06F21/64 ,  G07F17/3227

摘要： Embodiments include a method for configuring basic input/output system (BIOS) of a wagering game machine. The method can include: initializing a processor and chipset residing on an embedded computer module residing in the wagering game machine, wherein the BIOS resides on a carrier board connected to the embedded computer module; identifying, under control of code in the BIOS, the embedded computer module as a particular one of a plurality of embedded computer modules, wherein the BIOS includes code for configuring each of the plurality of embedded computer modules; initializing, using code of the BIOS configured for the particular one of the plurality of embedded computer modules, input/output devices connected to the carrier board and embedded computer module; launching, under control of the BIOS, an operating system in the wagering game machine; presenting a wagering game on the wagering game machine, wherein the presenting utilizes information received from the input/output devices.

摘要翻译： 实施例包括用于配置投注游戏机的基本输入/输出系统（BIOS）的方法。 该方法可以包括：初始化驻留在投注游戏机中的嵌入式计算机模块上的处理器和芯片组，其中BIOS驻留在连接到嵌入式计算机模块的载板上; 在所述BIOS中的代码控制下，将所述嵌入式计算机模块识别为多个嵌入式计算机模块中的特定一个，其中所述BIOS包括用于配置所述多个嵌入式计算机模块中的每一个的代码; 初始化使用为所述多个嵌入式计算机模块中的特定一个配置的BIOS的代码，连接到所述载板和嵌入式计算机模块的输入/输出设备; 在BIOS的控制下启动投注游戏机中的操作系统; 在投注游戏机上呈现投注游戏，其中呈现利用从输入/输出设备接收的信息。

公开(公告)号：US06438684B1

公开(公告)日：2002-08-20

申请号：US08963403

申请日：1997-11-03

申请人： Craig G. Mitchell ,  Michael P. Dempsey ,  Christian A. D'Souza ,  Chandra S. Pandoy ,  Scot W. Salzman

发明人： Craig G. Mitchell ,  Michael P. Dempsey ,  Christian A. D'Souza ,  Chandra S. Pandoy ,  Scot W. Salzman

IPC分类号： G06F15177

CPC分类号： G06F9/442 ,  G06F1/24

摘要： A system for shutting down and resetting an embedded system having a general purpose computing platform. A push button is provided for generating a push button reset signal to the shutdown and reset manager. The shutdown and reset manager receives the management reset signal and initiates a shutdown of the operating system. When the operating system has shutdown, the user presses the push button again. The second receipt of the push button reset signal initiates a hardware reset.

摘要翻译： 一种用于关闭和重置具有通用计算平台的嵌入式系统的系统。 提供按钮以产生到关闭和复位管理器的按钮复位信号。 关闭和复位管理器接收管理复位信号并启动操作系统的关闭。 当操作系统关闭时，用户再次按下按钮。 按钮复位信号的第二次接收启动硬件复位。

公开(公告)号：US5416776A

公开(公告)日：1995-05-16

申请号：US250276

申请日：1994-05-27

申请人： Russell C. Panzarella ,  Scot W. Salzman

发明人： Russell C. Panzarella ,  Scot W. Salzman

IPC分类号： G06F13/40 ,  H04L27/00 ,  H04M11/06 ,  H04B1/40

CPC分类号： H04M11/06 ,  G06F13/409 ,  H04L27/00

摘要： An improved backplane apparatus for transmitting signals to and from a modem system. The modem system includes more than one modem for transmitting data via at least one telephone line and via at least one network. The modem system has a first bus for management signal communication with the modems at a predetermined first data rate, and a second bus for transmitting data between the telephone line and the modems at a predetermined second data rate greater than the first data rate. The modem system also has a third bus for transmitting data between the modems and the network at a predetermined third data rate greater than the second data rate, and a fourth bus for distributing DC power and ground potential. The modem system defines a first impedance for terminating the first bus, a second impedance for terminating the second bus, and a third impedance for terminating the third bus. Finally, the modem system has structure for spacing the busses in layers in the backplane dependent on the data rate of the bus, and a plurality of connector assemblies for interconnecting circuit boards with the busses. Each connector assembly comprises an array of connectors arranged in rows and columns. The connectors are coupled to the busses according to a predetermined pattern dependent on the data rate of the bus, whereby the number of connector assemblies coupled to the first, second and third busses can be increased.

摘要翻译： 用于向/从调制解调器系统发送信号的改进的背板装置。 调制解调器系统包括多于一个的调制解调器，用于经由至少一个电话线路和经由至少一个网络传输数据。 调制解调器系统具有用于以预定的第一数据速率与调制解调器进行管理信号通信的第一总线，以及用于以大于第一数据速率的预定的第二数据速率在电话线路和调制解调器之间传送数据的第二总线。 调制解调器系统还具有用于以大于第二数据速率的预定的第三数据速率在调制解调器和网络之间传送数据的第三总线，以及用于分配直流电力和地电位的第四总线。 调制解调器系统定义用于终止第一总线的第一阻抗，用于终止第二总线的第二阻抗和用于终止第三总线的第三阻抗。 最后，调制解调器系统具有取决于总线的数据速率的背板中的层间隔布局的结构，以及用于将电路板与总线互连的多个连接器组件。 每个连接器组件包括以行和列布置的连接器阵列。 连接器根据总线的数据速率根据预定模式耦合到总线，由此可以增加耦合到第一，第二和第三总线的连接器组件的数量。