Method and circuits for associating a complex operator to each component of an input pattern presented to an artificial neural network
    1.
    发明授权
    Method and circuits for associating a complex operator to each component of an input pattern presented to an artificial neural network 失效
    用于将复杂算子与呈现给人造神经网络的输入模式的每个分量相关联的方法和电路

    公开(公告)号:US08027942B2

    公开(公告)日:2011-09-27

    申请号:US09951786

    申请日:2001-09-12

    CPC classification number: G06K9/6215 G06K9/6276 G06N3/063

    Abstract: The method and circuits of the present invention aim to associate a complex component operator (CC_op) to each component of an input pattern presented to an input space mapping algorithm based artificial neural network (ANN) during the distance evaluation process. A complex operator consists in the description of a function and a set of parameters attached thereto. The function is a mathematical entity (either a logic operator e.g. match(Ai,Bi), abs(Ai−Bi), . . . or an arithmetic operator, e.g. >,

    Abstract translation: 本发明的方法和电路旨在将复杂分量算子(CC_op)与在距离评估过程中呈现给基于输入空间映射算法的人造神经网络(ANN)的输入模式的每个分量相关联。 复杂的运算符在于对附加到其上的函数和一组参数的描述。 该函数是数学实体(逻辑运算符,例如匹配(Ai,Bi),abs(Ai-Bi),...或算术运算符,例如>,<,...。)或一组软件指令 有条件。 在第一实施例中,ANN被提供有存储所有CC_ops的ANN的所有神经元共用的全局存储器。 在另一个实施例中,CC_ops的集合存储在神经元的原型存储器中,使得全局存储器不再是物理上必需的。 根据本发明,存储的原型的组件现在可以指定不同性质的对象。 另外,这两种实现都显着减少神经元所需的组件数量,从而在ANN集成在硅芯片中时节省空间。

    Method to improve the data transfer rate between a computer and a neural network
    2.
    发明授权
    Method to improve the data transfer rate between a computer and a neural network 失效
    提高计算机和神经网络之间数据传输速率的方法

    公开(公告)号:US06983265B2

    公开(公告)日:2006-01-03

    申请号:US10316250

    申请日:2002-12-10

    CPC classification number: G06K9/6276 G06N3/04

    Abstract: A method is described to improve the data transfer rate between a personal computer or a host computer and a neural network implemented in hardware by merging a plurality of input patterns into a single input pattern configured to globally represent the set of input patterns. A base consolidated vector (U′*n) representing the input pattern is defined to describe all the vectors (Un, . . . , Un+6) representing the input patterns derived thereof (U′n, . . . , U′n+6) by combining components having fixed and ‘don't care’ values. The base consolidated vector is provided only once with all the components of the vectors. An artificial neural network (ANN) is then configured as a combination of sub-networks operating in parallel. In order to compute the distances with an adequate number of components, the prototypes are to include also components having a definite value and ‘don't care’ conditions. During the learning phase, the consolidated vectors are stored as prototypes. During the recognition phase, when a new base consolidated vector is provided to ANN, each sub-network analyses a portion thereof After computing all the distances, they are sorted one sub-network at a time to obtain the distances associated to each vector.

    Abstract translation: 描述了一种方法,以通过将多个输入模式合并为被配置为全局地表示该组输入模式的单个输入模式来改善个人计算机或主机计算机与硬件中实现的神经网络之间的数据传输速率。 定义表示输入模式的基本合并向量(U'* N n N)来描述所有向量(U N,N,N,N,N) 代表其导出的输入模式(U',N“,...,U”n + 6)的组合,通过组合具有固定的“不” 护理价值观。 基本合并向量仅与向量的所有分量一起提供。 然后将人造神经网络(ANN)配置为并行操作的子网络的组合。 为了用足够数量的组件计算距离,原型还包括具有确定值和“无关紧要”条件的组件。 在学习阶段,合并的向量存储为原型。 在识别阶段,当向ANN提供新的基本合并向量时,每个子网络分析其一部分。在计算所有距离之后,它们一次对一个子网进行排序,以获得与每个向量相关联的距离。

    Method and circuits for associating a norm to each component of an input pattern presented to a neural network
    3.
    发明授权
    Method and circuits for associating a norm to each component of an input pattern presented to a neural network 失效
    用于将范数与呈现给神经网络的输入模式的每个分量相关联的方法和电路

    公开(公告)号:US06782373B2

    公开(公告)日:2004-08-24

    申请号:US09682035

    申请日:2001-07-12

    CPC classification number: G06K9/6215 G06K9/6276 G06N3/063

    Abstract: The method and circuits of the present invention aim to associate a norm to each component of an input pattern presented to an input space mapping algorithm based artificial neural network (ANN) during the distance evaluation process. The set of norms, referred to as the “component” norms is memorized in specific memorization means in the ANN. In a first embodiment, the ANN is provided with a global memory, common for all the neurons of the ANN, that memorizes all the component norms. For each component of the input pattern, all the neurons perform the elementary (or partial) distance calculation with the corresponding prototype components stored therein during the distance evaluation process using the associated component norm. The distance elementary calculations are then combined using a “distance” norm to determine the final distance between the input pattern and the prototypes stored in the neurons. In another embodiment, the set of component norms is memorized in the neurons themselves in the prototype memorization means, so that the global memory is no longer physically necessary. This implementation allows to significantly optimize the consumed silicon area when the ANN is integrated in a silicon chip.

    Abstract translation: 本发明的方法和电路旨在将距离评估过程中给出的输入模式的每个分量与基于输入空间映射算法的人造神经网络(ANN)相关联。 被称为“组件”规范的一套规范被记录在ANN中的具体记忆手段中。 在第一实施例中,ANN被提供有存储ANN的所有神经元的全局存储器,其存储所有的分量规范。 对于输入模式的每个分量,所有神经元使用相关的分量范数在距离评估过程中,使用存储在其中的对应的原型分量执行基本(或部分)距离计算。 然后使用“距离”范数组合距离基本计算,以确定输入模式和存储在神经元中的原型之间的最终距离。 在另一个实施例中,组件规范的集合被存储在原型存储装置中的神经元本身中,使得全局存储器不再是物理上必需的。 当ANN集成在硅芯片中时,该实现允许显着优化消耗的硅面积。

    Method and circuits for performing the quick search of the minimum/maximum value among a set of numbers
    4.
    发明授权
    Method and circuits for performing the quick search of the minimum/maximum value among a set of numbers 失效
    用于在一组数字中快速搜索最小/最大值的方法和电路

    公开(公告)号:US06748405B2

    公开(公告)日:2004-06-08

    申请号:US09754639

    申请日:2001-01-04

    CPC classification number: G06F7/544 G06F7/22 G06F9/30021

    Abstract: In the search of the minimum value among a set of p Numbers coded on q bits, each Number is split into K sub-values coded on n bits (q>=K×n). Parameter K thus assigns a rank to each sub-value so that K slices of bits are formed wherein each slice is composed of sub-values of the same rank. Each sub-value is then encoded on m bits (m>n) using a “thermometric” coding technique. A parallel search is then performed on the first slice of encoded sub-values (MSBs) to determine the minimum sub-value of that slice. All the Numbers associated to sub-values that are greater than the minimum sub-value that has been evaluated are deselected. The evaluation process is continued the same way until the last slice (LSBs) has been processed. At the end of the evaluation process, the Number which remains selected has the minimum value. The response time (i.e. the number of processing steps) now only depends upon the number K of sub-values in which the Numbers have been split up. The method applies to search the maximum as well.

    Abstract translation: 在搜索在q位上编码的p个编码集合中的最小值时,每个数字被分割为以n位编码的K个子值(q> = Kxn)。 因此,参数K为每个子值分配等级,使得形成K个比特片,其中每个切片由相同等级的子值组成。 然后使用“温度测量”编码技术,以m位(m> n)对每个子值进行编码。 然后对编码子值(MSB)的第一切片执行并行搜索以确定该切片的最小子值。 所有与子值相关联的数字大于已评估的最小子值的数字将被取消选择。 评估过程以相同的方式继续,直到最后一个切片(LSB)被处理。 在评估过程结束时,保持选中的数字具有最小值。 响应时间(即处理步骤的数目)现在只取决于数字已被分割的子值的数量K. 该方法也适用于搜索最大值。

    Memory access system
    5.
    发明授权
    Memory access system 失效
    内存访问系统

    公开(公告)号:US06715104B2

    公开(公告)日:2004-03-30

    申请号:US09682119

    申请日:2001-07-24

    CPC classification number: G06F11/2094 G06F11/1402

    Abstract: A system for accessing a memory organized in memorization subsystems or memory blocks, e.g. standard Dual In-line Memory Modules, wherein the words to be stored are split into unitary elements so that several memorization subsystems are used to store one word and its associated Block Error Code (BEC) bits, is disclosed. The system includes a detector to detect a failure within a memorization subsystem. Insulator that are associated to each memorization subsystem insulate the failed memory block, and a new memorization subsystem is accessed in lieu of the failed one thanks to identification device which determine an available unfailed memory block. The user may replace the failed memory block without shutting down the memory device.

    Abstract translation: 用于访问存储在存储子系统或存储器块中的存储器的系统,例如存储器。 标准双列直插式存储器模块,其中要存储的字被分割为单一元件,以便使用多个存储子系统来存储一个字并且其相关联的块错误代码(BEC)位被公开。 该系统包括用于检测存储子系统中的故障的检测器。 与每个存储子系统相关联的绝缘体绝缘失效的存储器块,并且由于确定可用的未存储存储器块的识别装置,存储新的存储子系统以代替失败的存储器子系统。 用户可以在不关闭存储设备的情况下更换故障存储器块。

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