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17 条记录 (耗时 0.024 秒)

    Deskewing global clock skew using localized DLLs
    1.
    发明授权
    Deskewing global clock skew using localized DLLs 有权
    使用本地化DLL来消除全局时钟偏移

    公开(公告)号：US06686785B2

    公开(公告)日：2004-02-03

    申请号：US09975359

    申请日：2001-10-11

    申请人： Dean Liu ,  Tyler J. Thorp ,  Pradeep R. Trivedi ,  Gin S. Yee ,  Claude R. Gauthier

    发明人： Dean Liu ,  Tyler J. Thorp ,  Pradeep R. Trivedi ,  Gin S. Yee ,  Claude R. Gauthier

    IPC分类号： H03L706

    CPC分类号： H03L7/07 ,  G06F1/10 ,  H03L7/0814

    摘要： An integrated circuit has a plurality of sections, each having a phase detector and a control delay circuit. The phase detector, in response to a phase difference between a reference clock signal and a feedback signal from a portion of a clock grid, controls the delay of its associated clock delay circuit, which, in turn, outputs to the portion of the clock grid. The feedback signal to the phase detector may be connected to an output of a DLL or another portion of the clock grid controlled by a clock delay circuit not associated with the phase detector. Such an arrangement on the integrated circuit leads to clock grid skew reduction.

    摘要翻译： 集成电路具有多个部分，每个部分具有相位检测器和控制延迟电路。 相位检测器响应于参考时钟信号和来自时钟网格的一部分的反馈信号之间的相位差来控制其关联的时钟延迟电路的延迟，其又输出到时钟网格的一部分 。 到相位检测器的反馈信号可以连接到DLL或由与相位检测器不相关的时钟延迟电路控制的时钟网格的另一部分的输出。 集成电路上的这种布置导致时钟网格偏移减少。

    On-die thermal monitoring technique
    2.
    发明授权
    On-die thermal monitoring technique 有权
    模内热监测技术

    公开(公告)号：US06814485B2

    公开(公告)日：2004-11-09

    申请号：US10349645

    申请日：2003-01-23

    申请人： Claude R. Gauthier ,  Gin S. Yee

    发明人： Claude R. Gauthier ,  Gin S. Yee

    IPC分类号： G01K700

    CPC分类号： G01K7/01

    摘要： A method and apparatus for monitoring a temperature on an integrated circuit that includes a thin gate oxide transistor. A temperature monitoring system that includes a thick gate oxide transistor is provided. The temperature monitoring system includes a temperature independent voltage generator, a temperature dependent voltage generator that includes a thick gate oxide transistor, and a quantifier operatively connected to the temperature independent voltage generator and temperature dependent voltage generator.

    摘要翻译： 一种用于监测包括薄栅极氧化物晶体管的集成电路的温度的方法和装置。 提供了包括厚栅极氧化物晶体管的温度监测系统。 温度监测系统包括一个独立于温度的电压发生器，一个温度相关的电压发生器，它包括一个厚栅极氧化物晶体管，和一个与温度无关的电压发生器和与温度相关的电压发生器可操作地连接的量子

    IC analog debugging and calibration thereof
    3.
    发明授权
    IC analog debugging and calibration thereof 有权
    IC模拟调试和校准

    公开(公告)号：US07203613B1

    公开(公告)日：2007-04-10

    申请号：US10830881

    申请日：2004-04-23

    申请人： Gin S. Yee ,  Claude R. Gauthier

    发明人： Gin S. Yee ,  Claude R. Gauthier

    IPC分类号： G01R31/00

    CPC分类号： G01R19/252 ,  G01R31/316 ,  G01R31/31705

    摘要： An analog debugging block of an integrated circuit includes a multiplexor, a buffer, and a voltage-controlled oscillator. An analog voltage signal-of-interest is selectively passed through the multiplexor to the buffer. The buffer outputs an analog control voltage dependent on the selected analog voltage signal-of-interest. The analog control voltage serves as an input to the voltage-controlled oscillator and is used to control a frequency of a digital output signal generated from the voltage-controlled oscillator. The digital output signal from the voltage-controlled oscillator is driven off-chip, whereupon a frequency of the digital output signal is determined and compared against a collection of known frequencies that correspond to particular known voltages of the analog voltage signal-of-interest, thereby resulting in a determination of the value of the selected analog voltage signal-of-interest.

    摘要翻译： 集成电路的模拟调试块包括多路复用器，缓冲器和压控振荡器。 选择性地将模拟电压信号信号通过多路复用器传送到缓冲器。 缓冲器输出取决于所选模拟电压信号的模拟控制电压。 模拟控制电压用作压控振荡器的输入，用于控制从压控振荡器产生的数字输出信号的频率。 来自压控振荡器的数字输出信号被驱动离开芯片，由此确定数字输出信号的频率并将其与对应于模拟电压感兴趣信号的特定已知电压的已知频率的集合进行比较， 从而导致所选择的模拟电压信号信号的值的确定。

    Compensation technique to mitigate aging effects in integrated circuit components
    4.
    发明授权
    Compensation technique to mitigate aging effects in integrated circuit components 有权
    补偿技术，以减轻集成电路元件的老化效应

    公开(公告)号：US07129800B2

    公开(公告)日：2006-10-31

    申请号：US10771989

    申请日：2004-02-04

    申请人： Claude R. Gauthier ,  Pradeep R. Trivedi ,  Raymond A. Heald ,  Gin S. Yee

    发明人： Claude R. Gauthier ,  Pradeep R. Trivedi ,  Raymond A. Heald ,  Gin S. Yee

    IPC分类号： H03L1/00

    CPC分类号： H03L7/18 ,  G01R31/31727 ,  G06F2217/76 ,  H03L7/0812 ,  H03L7/0893

    摘要： A method and apparatus for compensating for age related degradation in the performance of integrated circuits. In one embodiment, the phase-locked loop (PLL) charge pump is provided with multiple legs that can be selectively enabled or disabled to compensate for the effects of aging. In an alternate embodiment, the power supply voltage control codes can be increased or decreased to compensate for aging effects. In another embodiment, a ring oscillator is used to approximate the effects of NBTI. In this embodiment, the frequency domain is converted to time domain using digital counters and programmable power supply control words are used to change the operating parameters of the power supply to compensate for aging effects.

    摘要翻译： 一种用于补偿集成电路性能的年龄相关退化的方法和装置。 在一个实施例中，锁相环（PLL）电荷泵设置有多个支脚，其可以选择性地启用或禁用以补偿老化的影响。 在替代实施例中，可以增加或减少电源电压控制代码以补偿老化效应。 在另一个实施例中，环形振荡器用于近似NBTI的影响。 在本实施例中，使用数字计数器将频域转换为时域，并且使用可编程电源控制字来改变电源的操作参数以补偿老化效应。

    Embedded integrated circuit aging sensor system
    5.
    发明授权
    Embedded integrated circuit aging sensor system 有权
    嵌入式集成电路老化传感器系统

    公开(公告)号：US07054787B2

    公开(公告)日：2006-05-30

    申请号：US10349854

    申请日：2003-01-23

    申请人： Claude R. Gauthier ,  Pradeep R. Trivedi ,  Gin S. Yee

    发明人： Claude R. Gauthier ,  Pradeep R. Trivedi ,  Gin S. Yee

    IPC分类号： G06F11/00

    CPC分类号： G01R31/2829

    摘要： A method and apparatus for sensing an aging effect on an integrated circuit using a sensor disposed on the integrated circuit and arranged to generate an output dependent on a condition of an element within the sensor. A processor operatively connected to the sensor is arranged to indicate a code dependent the output.

    摘要翻译： 用于使用设置在集成电路上的传感器来感测对集成电路的老化效应的方法和装置，并且被布置成根据传感器内的元件的状况产生输出。 可操作地连接到传感器的处理器被布置成指示依赖于输出的代码。

    On-chip temperature measurement technique
    6.
    发明授权
    On-chip temperature measurement technique 有权

    公开(公告)号：US06934652B2

    公开(公告)日：2005-08-23

    申请号：US10704843

    申请日：2003-11-10

    申请人： Claude R. Gauthier ,  Gin S. Yee

    发明人： Claude R. Gauthier ,  Gin S. Yee

    IPC分类号： G01K15/00

    CPC分类号： G01K15/00

    摘要： A temperature monitoring technique that eliminates the need for bipolar devices. In one embodiment of the present invention, a long-channel MOS transistor is configured in a diode connection to sense change in temperature. The diode drives a linear regulator and an oscillator. The oscillator in turn drives a counter, which counts pulses for a fixed period of time. The system clock on the chip is used as a temperature-independent frequency to generate a count. The temperature-dependent frequency is counted for a fixed number of system clock cycles. The present invention eliminates band gap circuitry currently used in most thermal sensing devices to provide a temperature-independent reference.

    Clock frequency multiplier
    9.
    发明授权
    Clock frequency multiplier 有权
    时钟倍频器

    公开(公告)号：US06815991B2

    公开(公告)日：2004-11-09

    申请号：US10339214

    申请日：2003-01-09

    申请人： Gin S. Yee ,  Shaoping Ge

    发明人： Gin S. Yee ,  Shaoping Ge

    IPC分类号： H03K504

    CPC分类号： H03K5/00006 ,  H03K3/033

    摘要： A clock frequency multiplier design is provided. The clock frequency multiplier includes an input stage arranged to receive an input clock signal, a first clock cycle generator stage operatively connected to the input stage and arranged to generate a low pulse on a first signal dependent on a low phase of the input clock signal, a second clock cycle generator stage operatively connected to the input stage and arranged to generate a low pulse on a second signal dependent on a high phase of the input clock signal, and an output stage operatively connected to the first clock cycle generator stage and the second clock cycle generator stage and arranged to output a high pulse on an output clock signal for every low pulse on the first signal and the second signal.

    Dual edge-triggered flip-flop design with asynchronous programmable reset
    10.
    发明授权
    Dual edge-triggered flip-flop design with asynchronous programmable reset 有权
    具有异步可编程复位的双边沿触发触发器设计

    公开(公告)号：US06720813B1

    公开(公告)日：2004-04-13

    申请号：US10390286

    申请日：2003-03-17

    申请人： Gin S. Yee ,  Pradeep R. Trivedi ,  Joseph R. Siegel

    发明人： Gin S. Yee ,  Pradeep R. Trivedi ,  Joseph R. Siegel

    IPC分类号： H03K3037

    CPC分类号： H03K3/037

    摘要： A dual edge-triggered flip-flop that may be programmably reset independent of a clock signal is provided. Using an externally generated reset value, the dual edge-triggered flip-flop may be asynchronously programmed to reset to either a logical high or a logical low. Further, a dual edge-triggered flip-flop that may be set to multiple triggering modes is provided. Using an externally generated enable signal, the dual edge-triggered flip-flop may be set to function as a single edge-triggered or a dual edge-triggered device. Thus, the dual edge-triggered flip-flop may be used multiple types of computing environments.

    摘要翻译： 提供可以独立于时钟信号可编程地复位的双边沿触发触发器。 使用外部产生的复位值，双边沿触发的触发器可以异步编程以复位为逻辑高或逻辑低电平。 此外，提供可以设置为多个触发模式的双边沿触发触发器。 使用外部产生的使能信号，双边沿触发触发器可以被设置为单边沿触发或双边沿触发器件。 因此，双边沿触发的触发器可以用于多种类型的计算环境。