公开(公告)号：US20050280725A1

公开(公告)日：2005-12-22

申请号：US11119223

申请日：2005-04-29

申请人： Giuseppe Spampinato ,  Francesco Pappalardo ,  Paolo Fodera ,  Francesco Virlinzi ,  Alessandro Capra

发明人： Giuseppe Spampinato ,  Francesco Pappalardo ,  Paolo Fodera ,  Francesco Virlinzi ,  Alessandro Capra

IPC分类号： G06T1/20 ,  G06T1/60 ,  G06T3/40 ,  H04N5/335

CPC分类号： G06T3/4015 ,  G06T1/20

摘要： A color image processing pipeline performs an interpolation on color data to generate triplets located at distinct pixel locations. The pipeline includes defect correction and image enhancement blocks having a first color interpolation block for generating RGB information for each pixel of an input image pixel pattern, and a second color interpolation block for receiving the RGB information to provide enhanced RGB pattern pixels. Dedicated line memories and delay circuits associated with the defect correction and image enhancement blocks permit real-time processing of pixel data. First and second read/write buffers store a subset or pixel block of the image data, and invert a scanning mode of pixel data being fed to the dedicated line memories and delay circuits associated to at least the first color interpolation block, from row-wise to column-wise, for each subset of data to be stored therein.

摘要翻译： 彩色图像处理流水线对颜色数据执行内插以产生位于不同像素位置处的三元组。 该管线包括缺陷校正和图像增强块，其具有用于产生输入图像像素图案的每个像素的RGB信息的第一颜色内插块和用于接收RGB信息以提供增强的RGB图案像素的第二颜色内插块。 与缺陷校正和图像增强块相关联的专用行存储器和延迟电路允许像素数据的实时处理。 第一和第二读/写缓冲器存储图像数据的子集或像素块，并反转正被馈送到专用行存储器的像素数据的扫描模式和与至少第一颜色内插块相关联的延迟电路， 对于要存储在其中的数据的每个子集，按列逐列。

公开(公告)号：US07397944B2

公开(公告)日：2008-07-08

申请号：US11119223

申请日：2005-04-29

申请人： Giuseppe Spampinato ,  Francesco Pappalardo ,  Paolo Antonino Foderá ,  Francesco Virlinzi ,  Alessandro Capra

发明人： Giuseppe Spampinato ,  Francesco Pappalardo ,  Paolo Antonino Foderá ,  Francesco Virlinzi ,  Alessandro Capra

IPC分类号： G06K9/00 ,  G06K9/36 ,  G06F3/038 ,  H04N9/04

CPC分类号： G06T3/4015 ,  G06T1/20

摘要： A color image processing pipeline performs an interpolation on color data to generate triplets located at distinct pixel locations. The pipeline includes defect correction and image enhancement blocks having a first color interpolation block for generating RGB information for each pixel of an input image pixel pattern, and a second color interpolation block for receiving the RGB information to provide enhanced RGB pattern pixels. Dedicated line memories and delay circuits associated with the defect correction and image enhancement blocks permit real-time processing of pixel data. First and second read/write buffers store a subset or pixel block of the image data, and invert a scanning mode of pixel data being fed to the dedicated line memories and delay circuits associated to at least the first color interpolation block, from row-wise to column-wise, for each subset of data to be stored therein.

摘要翻译： 彩色图像处理流水线对颜色数据执行内插以产生位于不同像素位置处的三元组。 该管线包括缺陷校正和图像增强块，其具有用于产生输入图像像素图案的每个像素的RGB信息的第一颜色内插块和用于接收RGB信息以提供增强的RGB图案像素的第二颜色内插块。 与缺陷校正和图像增强块相关联的专用行存储器和延迟电路允许像素数据的实时处理。 第一和第二读/写缓冲器存储图像数据的子集或像素块，并反转正被馈送到专用行存储器的像素数据的扫描模式和与至少第一颜色内插块相关联的延迟电路， 对于要存储在其中的数据的每个子集，按列逐列。

公开(公告)号：US20060245642A1

公开(公告)日：2006-11-02

申请号：US11119154

申请日：2005-04-29

申请人： Giuseppe Spampinato ,  Alessandro Capra ,  Francesco Pappalardo

发明人： Giuseppe Spampinato ,  Alessandro Capra ,  Francesco Pappalardo

IPC分类号： G06K9/00

CPC分类号： G06T1/60

摘要： An image generating pipeline (IGP) includes a digital signal processor for implementing processing blocks connected in cascade for processing an input image that includes an array of raw pixel values to generated a color image that includes an array of reconstructed pixel values. A memory is coupled to the digital signal processor for storing the raw pixel values and the array of reconstructed pixel values. The digital signal processor includes a data cache, and the raw pixel values of the input image are processed through the processing blocks in sub-arrays having fractional dimensions of the pixel-dimensions of the whole image array. The sub-arrays include an input sub-array of pixel values being loaded from the memory for defining a working window. The sub-arrays of raw pixel values have a row-wise dimension of at least a fraction of a full row of the input-image, and a column-wise dimension equal to or larger than a column-wise filtering action of a respective processing block to which the input sub-array is input. The digital signal processor outputs at least one fraction of full rows of completely reconstructed pixel values of the input image for storing in the memory.

摘要翻译： 图像产生管线（IGP）包括用于实现级联连接的处理块的数字信号处理器，用于处理包括原始像素值阵列的输入图像，以产生包括重构像素值阵列的彩色图像。 存储器耦合到数字信号处理器，用于存储原始像素值和重构像素值的阵列。 数字信号处理器包括数据高速缓存，并且通过具有整个图像阵列的像素维度的分数维的子阵列中的处理块来处理输入图像的原始像素值。 子阵列包括从存储器加载的用于定义工作窗口的像素值的输入子阵列。 原始像素值的子阵列具有至少输入图像的完整行的一小部分的行方向尺寸，以及等于或大于相应处理的逐列滤波动作的列方向尺寸 输入子数组输入的块。 数字信号处理器输出用于存储在存储器中的输入图像的完整重建像素值的至少一部分完整重建的像素值。

公开(公告)号：US07733396B2

公开(公告)日：2010-06-08

申请号：US10696396

申请日：2003-10-29

申请人： Francesco Pappalardo ,  Alessandro Capra ,  Massimo Mancuso ,  Hervé Broquin ,  Paolo Antonino Fodera ,  Elena Salurso

发明人： Francesco Pappalardo ,  Alessandro Capra ,  Massimo Mancuso ,  Hervé Broquin ,  Paolo Antonino Fodera ,  Elena Salurso

IPC分类号： H04N3/14 ,  H04N5/335 ,  H04N9/04 ,  H04N7/12 ,  H04N11/02 ,  H04N11/04

CPC分类号： H04N1/648

摘要： Digital video signals, such as the signals generated by an image sensor in a Bayer format, are converted into an encoded format. In the Bayer format, the pixels of each line are alternately coded with two colors, and then converted into the encoded format. In the encoded format, the pixels of the digital video signals are reordered into sets of adjacent pixels, such that the sets group pixels coded with the same color. The encoded signal data results in a reduced switching activity when transmitted over a bus.

摘要翻译： 诸如由拜耳格式的图像传感器产生的信号的数字视频信号被转换成编码格式。 在拜耳格式中，每行的像素被交替地用两种颜色编码，然后被转换为编码格式。 在编码格式中，将数字视频信号的像素重新排列成相邻像素的集合，使得组合像素以相同颜色编码。 编码的信号数据在总线上传输时导致切换活动降低。

公开(公告)号：US09378077B2

公开(公告)日：2016-06-28

申请号：US12850056

申请日：2010-08-04

申请人： Francesco Pappalardo ,  Giuseppe Notarangelo ,  Elio Guidetti

发明人： Francesco Pappalardo ,  Giuseppe Notarangelo ,  Elio Guidetti

IPC分类号： G06F11/00 ,  G06F11/07 ,  G06F11/16 ,  H03K19/007

CPC分类号： G06F11/0751 ,  G06F11/1608 ,  G06F11/1629 ,  H03K19/007

摘要： Errors induced by noise pulses in digital electronic circuits clocked with a clock signal are detected by providing at least one additional clock signal offset in time with respect to the clock signal by a given interval, and performing for at least one component of the circuit a comparison of correspondence between two versions of one and the same signal. The comparison is clocked by the additional clock signal and the absence of correspondence between the two versions of said signal identifies an error induced in the circuit by a noise pulse.

摘要翻译： 通过以时钟信号计时的数字电子电路中的噪声脉冲引起的误差是通过在给定的时间间隔内为时钟信号提供至少一个额外的时钟信号偏移来检测的，并且对电路的至少一个分量执行比较 两个版本之间的对应关系和相同的信号。 比较由附加时钟信号计时，并且所述信号的两个版本之间不存在对应关系，通过噪声脉冲识别电路中感应的误差。

公开(公告)号：US07480354B2

公开(公告)日：2009-01-20

申请号：US11051561

申请日：2005-02-04

申请人： Francesco Rimi ,  Alberto Serratore ,  Giuseppe Avellone ,  Francesco Pappalardo ,  Agostino Galluzzo

发明人： Francesco Rimi ,  Alberto Serratore ,  Giuseppe Avellone ,  Francesco Pappalardo ,  Agostino Galluzzo

IPC分类号： H03D1/00 ,  H04B7/216

CPC分类号： H04B1/7083 ,  H04B1/70735 ,  H04B2201/7071

摘要： In order to perform, according to a received signal (r), a channel-estimation procedure and a cell-search procedure in cellular communication systems, there are executed at least one first operation of correlation of said received signal (r) with secondary synchronization codes (SSC) and a second operation of correlation of said received signal (r) with known midamble codes (mid, MPL, MPS), whilst said channel-estimation procedure comprises a third operation of correlation of at least part of said received signal (r) with known midamble codes (mid, MPL, MPS), said first, second, and third correlation operation being executed by sending at least part (emidamble) of said received signal (r) to an input of a correlation bank. There are envisaged the operations of: sending, in a first time interval, the received signal (r) to said correlation bank for executing the first operation of correlation of said received signal (r) with secondary synchronization codes (SSC); sending, in a second time interval, at least part (emidamble) of said received signal (r) to said same correlation bank for executing the second operation of correlation of said received signal (r) with known midamble codes (mid, MPL, MPS); sending, in a second time interval, the received signal (r) to said same correlation bank for executing the third operation of correlation of at least part (emidamble) of said received signal (r) with known midamble codes (mid, MPL, MPS). Possible application is in mobile communication systems based upon standards such as UMTS, CDMA2000, IS95 or WBCDMA.

摘要翻译： 为了根据接收到的信号（r）执行蜂窝通信系统中的信道估计过程和小区搜索过程，执行所述接收信号（r）与辅助同步的相关的至少一个第一操作 代码（SSC）和所述接收信号（r）与已知中间码（mid，MPL，MPS）的相关的第二操作，而所述信道估计过程包括所述接收信号的至少一部分 所述第一，第二和第三相关运算是通过将所述接收信号（r）的至少一部分（emidamble）发送到相关库的输入来执行的。 设想了以下操作：在第一时间间隔中将接收信号（r）发送到所述相关库，以执行所述接收信号（r）与辅同步码（SSC）的相关的第一操作; 在第二时间间隔中将所述接收信号（r）的至少一部分（emidamble）发送到所述相关相关库，以执行所述接收信号（r）与已知中间码（mid，MPL，MPS）的相关性的第二操作 ）; 将所接收的信号（r）在第二时间间隔中发送到所述相关相关库，以执行所述接收信号（r）的至少部分（emidamble）与已知中间码（mid，MPL，MPS）的相关的第三操作 ）。 可能的应用是基于UMTS，CDMA2000，IS95或WBCDMA等标准的移动通信系统。

公开(公告)号：US20080016317A1

公开(公告)日：2008-01-17

申请号：US11768462

申请日：2007-06-26

申请人： Francesco Pappalardo ,  Giuseppe Notarangelo ,  Elena Salurso ,  Elio Guidetti

发明人： Francesco Pappalardo ,  Giuseppe Notarangelo ,  Elena Salurso ,  Elio Guidetti

IPC分类号： G06F15/00

CPC分类号： G06F12/084 ,  G06F12/0886 ,  Y02D10/13

摘要： A data cache memory coupled to a processor including processor clusters are adapted to operate simultaneously on scalar and vectorial data by providing data locations in the data cache memory for storing data for processing. The data locations are accessed either in a scalar mode or in a vectorial mode. This is done by explicitly mapping the data locations that are scalar and the data locations that are vectorial.

摘要翻译： 耦合到包括处理器集群的处理器的数据高速缓冲存储器适于通过在数据高速缓冲存储器中提供用于存储用于处理的数据的数据位置同时操作标量和矢量数据。 数据位置以标量模式或矢量模式进行访问。 这通过明确地映射标量的数据位置和矢量的数据位置来完成。

公开(公告)号：US20050227725A1

公开(公告)日：2005-10-13

申请号：US11051561

申请日：2005-02-04

申请人： Francesco Rimi ,  Alberto Serratore ,  Giuseppe Avellone ,  Francesco Pappalardo ,  Agostino Galluzzo

发明人： Francesco Rimi ,  Alberto Serratore ,  Giuseppe Avellone ,  Francesco Pappalardo ,  Agostino Galluzzo

IPC分类号： H04B1/707 ,  H04B7/00

CPC分类号： H04B1/7083 ,  H04B1/70735 ,  H04B2201/7071

摘要： In order to perform, according to a received signal (r), a channel-estimation procedure and a cell-search procedure in cellular communication systems, there are executed at least one first operation of correlation of said received signal (r) with secondary synchronization codes (SSC) and a second operation of correlation of said received signal (r) with known midamble codes (mid, MPL, MPS), whilst said channel-estimation procedure comprises a third operation of correlation of at least part of said received signal (r) with known midamble codes (mid, MPL, MPS), said first, second, and third correlation operation being executed by sending at least part (emidamble) of said received signal (r) to an input of a correlation bank. There are envisaged the operations of: sending, in a first time interval, the received signal (r) to said correlation bank for executing the first operation of correlation of said received signal (r) with secondary synchronization codes (SSC); sending, in a second time interval, at least part (emidamble) of said received signal (r) to said same correlation bank for executing the second operation of correlation of said received signal (r) with known midamble codes (mid, MPL, MPS); sending, in a second time interval, the received signal (r) to said same correlation bank for executing the third operation of correlation of at least part (emidamble) of said received signal (r) with known midamble codes (mid, MPL, MPS). Possible application is in mobile communication systems based upon standards such as UMTS, CDMA2000, IS95 or WBCDMA.

摘要翻译： 为了根据接收到的信号（r）执行蜂窝通信系统中的信道估计过程和小区搜索过程，执行所述接收信号（r）与辅助同步的相关的至少一个第一操作 代码（SSC）和所述接收信号（r）与已知中间码（mid，MPL，MPS）的相关的第二操作，而所述信道估计过程包括所述接收信号的至少一部分 所述第一，第二和第三相关运算是通过将所述接收信号（r）的至少一部分（e midamble）发送到 相关银行的输入。 设想了以下操作：在第一时间间隔中将接收信号（r）发送到所述相关库，以执行所述接收信号（r）与辅同步码（SSC）的相关的第一操作; 在第二时间间隔中将所述接收信号（r）的至少一部分（e中间码）发送到所述相关相关库，以执行所述接收信号（r）与已知的 中号码（中，MPL，MPS）; 在第二时间间隔中将接收到的信号（r）发送到所述相关相关库，以执行所述接收信号（r）的至少部分（e> mid amble amble amble amble）与已知的 midamble码（mid，MPL，MPS）。 可能的应用是基于UMTS，CDMA2000，IS95或WBCDMA等标准的移动通信系统。

公开(公告)号：US06898076B2

公开(公告)日：2005-05-24

申请号：US10242296

申请日：2002-09-12

申请人： Francesco Pappalardo ,  Luigi Mantellassi

发明人： Francesco Pappalardo ,  Luigi Mantellassi

IPC分类号： G06F1/16

CPC分类号： G06F1/1632 ,  G06F1/1626

摘要： A modular information processing system is disclosed. The system includes an expansion device that embeds at least one internal peripheral without a controller and/or at least one port for connecting an external peripheral. The system further includes a hand-held computer that embeds control circuitry including at least one controller for the at least one internal peripheral or at least one external peripheral, and an interface for coupling the hand-held computer to the expansion device in a removable manner. In a mobile operating condition in which the hand-held computer is not coupled to the expansion device, the processing circuitry controls the hand-held computer. In an expanded operating condition in which the hand-held computer is coupled to the expansion device, the processing circuitry controls a personal computer formed by the hand-held computer and the expansion device. Also provided are a hand-held computer and an expansion device for use in modular information processing systems.

摘要翻译： 公开了一种模块化信息处理系统。 该系统包括在没有控制器的情况下嵌入至少一个内部外围设备的扩展设备和/或用于连接外部外围设备的至少一个端口。 该系统还包括嵌入控制电路的手持计算机，该控制电路包括用于至少一个内部外围设备或至少一个外部外围设备的至少一个控制器，以及用于以可拆卸的方式将手持计算机连接到扩展装置的接口 。 在手持计算机没有耦合到扩展装置的移动操作条件下，处理电路控制手持计算机。 在手持计算机耦合到扩展装置的扩展操作条件下，处理电路控制由手持计算机和扩展装置形成的个人计算机。 还提供了一种用于模块化信息处理系统的手持计算机和扩展装置。

公开(公告)号：US08126084B2

公开(公告)日：2012-02-28

申请号：US12844451

申请日：2010-07-27

申请人： Giuseppe Visalli ,  Francesco Pappalardo

发明人： Giuseppe Visalli ,  Francesco Pappalardo

IPC分类号： H04L27/00 ,  H03K9/00

CPC分类号： H04L12/2856

摘要： Embodiment for forming an aggregate signal from a plurality of starting signals, comprising: acquiring said starting signals through respective sensors of a homogeneous sensors group; converting acquired signals in respective digital signals having data represented with a predetermined bits number; processing the digital signals to form aggregate signal. The processing step comprises the operations of: modifying digital signals changing the data format of each such digital signals from a first format to a second format, each data in the second format having been obtained from a respective data in the first format through an operation of permuting the bits position according to a permutation scheme associated with said data and to the specific digital signal comprising that data; forming aggregate signal obtaining said aggregate signal data by means of a bitwise logic operator acting upon said modified digital signal respective data.

摘要翻译： 用于从多个起始信号形成聚集信号的实施例，包括：通过均匀传感器组的相应传感器获取所述起始信号; 在具有以预定比特数表示的数据的各个数字信号中转换获取的信号; 处理数字信号以形成聚合信号。 处理步骤包括以下操作：修改将每个这样的数字信号的数据格式从第一格式改变为第二格式的数字信号，第二格式中的每个数据是从第一格式的相应数据获得的， 根据与所述数据相关联的置换方案和包括该数据的特定数字信号来排列比特位置; 形成通过对所述修改的数字信号相应数据作用的按位逻辑运算器获得所述聚合信号数据的聚合信号。