公开(公告)号：US12243614B2

公开(公告)日：2025-03-04

申请号：US18046961

申请日：2022-10-17

Applicant: GlobalFoundries U.S. Inc.

Inventor： Siva Kumar Chinthu ,  Suresh Pasupula ,  Devesh Dwivedi ,  Chunsung Chiang

IPC: G11C7/06 ,  G11C7/10 ,  G11C7/12

Abstract: Embodiments of the disclosure provide memory circuit, a sense amplifier and associated method for reading a resistive state in a memory device. The sense amplifier includes a bit cell configurable to a high or low resistance state; a sensing circuit that detects a voltage drop across the bit cell in response to an applied read current during a read operation and generates a high or low logic output at an output node; and a pulse generation circuit that increases the applied read current with an injected current pulse when a low to high transition of the resistive state of the bit cell is detected.

公开(公告)号：US20240127868A1

公开(公告)日：2024-04-18

申请号：US18046961

申请日：2022-10-17

Applicant: GlobalFoundries U.S. Inc.

Inventor： Siva Kumar Chinthu ,  Suresh Pasupula ,  Devesh Dwivedi ,  Chunsung Chiang

IPC: G11C7/06 ,  G11C7/10 ,  G11C7/12

CPC classification number: G11C7/067 ,  G11C7/109 ,  G11C7/12

Abstract: Embodiments of the disclosure provide memory circuit, a sense amplifier and associated method for reading a resistive state in a memory device. The sense amplifier includes a bit cell configurable to a high or low resistance state; a sensing circuit that detects a voltage drop across the bit cell in response to an applied read current during a read operation and generates a high or low logic output at an output node; and a pulse generation circuit that increases the applied read current with an injected current pulse when a low to high transition of the resistive state of the bit cell is detected.