公开(公告)号：US20240028811A1

公开(公告)日：2024-01-25

申请号：US17813344

申请日：2022-07-19

Applicant: GlobalFoundries U.S. Inc.

Inventor： Alain F. Loiseau ,  Romain H.A. Feuillette ,  Mujahid Muhammad

IPC: G06F30/398 ,  G06F30/392

CPC classification number: G06F30/398 ,  G06F30/392

Abstract: A process design kit (PDK) is supplied to a layout design tool. The PDK includes parameterized cells (Pcells) adapted to cause the layout design tool to automatically add labels to device layouts in the graphic design system (GDS) file that is being created by the layout design tool. Each corresponding label lists parameters used when creating the corresponding device layout. The GDS file is receive back from the layout design tool. The parameters from the labels is applied to corresponding ones of the Pcells within the PDK to create a device verification layout for each of the device layouts in the GDS file. Each of the device layouts in the GDS file is compared to a corresponding device verification layout. The device layouts within the GDS file that fail to match the corresponding device verification layout are thereby identified.

公开(公告)号：US20250006650A1

公开(公告)日：2025-01-02

申请号：US18341893

申请日：2023-06-27

Applicant: GlobalFoundries U.S. Inc.

Inventor： Alain F. Loiseau ,  Romain H.A. Feuillette ,  Mujahid Muhammad ,  Peter T. Coutu

IPC: H01L23/544 ,  G01R31/28

Abstract: An integrated circuit (IC) includes a plurality of metal layers, and a machine-readable code in a selected metal layer of the plurality of metal layers. A wafer includes a plurality of the ICs. An IC wafer testing system includes a scanner configured to read the machine-readable code in the metal layer of the IC in the wafer, and a tester configured to perform testing on the IC in the wafer based on testing information obtained from storage based on the machine-readable code. A method may include forming the IC including a plurality of metal layers and forming a selected metal layer of the IC including the machine-readable code in metal in the selected metal layer. The method may further include testing the IC. The machine-readable code reduces the complexity and time needed to setup and test an IC in a wafer.