公开(公告)号：US09563588B1

公开(公告)日：2017-02-07

申请号：US14208644

申请日：2014-03-13

Applicant: Google Inc.

Inventor： Michael Roger Marty ,  Joel Scherpelz

IPC: G06F13/32 ,  G06F9/52 ,  G06F9/50 ,  G06F9/54 ,  G06F9/48 ,  G06F13/24

CPC classification number: G06F13/32 ,  G06F9/4812 ,  G06F9/4843 ,  G06F9/5005 ,  G06F9/52 ,  G06F9/54 ,  G06F13/24 ,  G06F2213/2418

Abstract: The present disclosure provides methods and systems to allow user space applications running on different cores to efficiently communicate interrupts between each other without have to enter an OS kernel. In one aspect, a hardware device for delivering inter-processor interrupts is provided. The hardware device includes a memory having a memory space that corresponds to a virtual memory space of a first guest process and a controller coupled to the memory. The controller may be configured to detect when interrupt information is recorded in the memory space. In that regard, the interrupt information is directed to a second guest process associated with a particular CPU core. In response to detecting interrupt information recorded in the memory space, the controller is configured to cause the second guest process to run on a different CPU core without making an operating system call.

Abstract translation: 本公开提供了允许在不同核上运行的用户空间应用以有效地在彼此之间通信中断而不必进入OS内核的方法和系统。 在一个方面，提供了用于递送处理器间中断的硬件设备。 硬件设备包括具有对应于第一访客处理的虚拟存储器空间的存储器空间和耦合到存储器的控制器的存储器。 控制器可以被配置为检测中断信息何时被记录在存储器空间中。 在这方面，中断信息被引导到与特定CPU核心相关联的第二访客进程。 响应于检测到记录在存储器空间中的中断信息，控制器被配置为使得第二客户进程在不进行操作系统调用的情况下在不同的CPU内核上运行。

公开(公告)号：US20180191623A1

公开(公告)日：2018-07-05

申请号：US15393529

申请日：2016-12-29

Applicant: Google Inc.

Inventor： Michael Marty ,  Joel Scherpelz ,  Marc de Kruijf ,  Christopher Alfeld

IPC: H04L12/859 ,  H04L12/26 ,  H04L12/863 ,  H04L12/24

Abstract: A computing system dedicates one or more processing units, such as cores, for the purposes of packet processing software, wherein other processing units simultaneously run application software. In some examples, the system uses dynamic load information to dynamically increase and decrease the number of processing units dedicated to packet processing. The system may further include a mechanism for establishing shared-memory regions for interacting with other applications' users. The shared memory mechanisms provide an abstraction of per-application “command” and “completion queues”. The system may poll per-application command queues for detecting the arrival of new requests. The mechanism also provides detection of application termination, as well as an ability for an application to expose portions of its address space for the reception and transmission of data. In some examples, the system further includes a framework for executing software-defined handlers inline with threads that run packet processing and transport software.