公开(公告)号：US20060209898A1

公开(公告)日：2006-09-21

申请号：US11348417

申请日：2006-02-07

申请人： Youssef Abdelilah ,  Gordon Davis ,  Jeffrey Derby ,  Dongming Hwang ,  Clark Jeffries ,  Malcolm Ware ,  Hua Ye

发明人： Youssef Abdelilah ,  Gordon Davis ,  Jeffrey Derby ,  Dongming Hwang ,  Clark Jeffries ,  Malcolm Ware ,  Hua Ye

IPC分类号： H04J3/18

CPC分类号： H04L47/10 ,  H04L12/6418 ,  H04L29/06027 ,  H04L47/12 ,  H04L47/2425 ,  H04L47/263 ,  H04L47/70 ,  H04L47/745 ,  H04L47/748 ,  H04L47/762 ,  H04L65/1009 ,  H04L65/607 ,  H04L65/80 ,  H04L2012/6481 ,  H04L2012/6497

摘要： A codec detects congestion in a packet network and responds via a session control protocol to re-negotiate codec-type and/or parameters with the receiving codec to reduce bit rate for supporting a session. Once the connection and session are established, encoded packets start flowing between the two codecs. A control entity sends and receives network congestion control packets periodically in the session. The congestion control packets provide a “heartbeat” signal to the receiving codec. When the network is not congested, all “heartbeat” packets will be passed through the network. As network congestion increases, routers within the network discard excess packets to prevent network failure. The codecs respond to the missing packets by slowing down the bit rate or proceeding to renegotiate a lower bit rate via the session control protocol. If there are no missing packets, the codecs detect if the session is operating at the highest bit rate, and if not, re-negotiate a higher bit rate.

摘要翻译： 编解码器检测分组网络中的拥塞，并通过会话控制协议进行响应，以使用接收编解码器重新协商编解码器类型和/或参数，以减少支持会话的比特率。 一旦建立了连接和会话，编码的数据包将在两个编解码器之间开始流动。 控制实体在会话中定期发送和接收网络拥塞控制报文。 拥塞控制分组向接收编解码器提供“心跳”信号。 当网络不拥塞时，所有“心跳”数据包将通过网络传递。 随着网络拥塞的增加，网络内的路由器丢弃多余的数据包，防止网络故障。 编解码器通过减慢比特率或通过会话控制协议进行重新协商较低的比特率来响应丢失的分组。 如果没有丢失数据包，则编解码器检测会话是否以最高比特率运行，如果不是，则重新协商更高的比特率。

公开(公告)号：US20080069194A1

公开(公告)日：2008-03-20

申请号：US11945213

申请日：2007-11-26

申请人： Gordon DAVIS ,  Jeffrey Derby ,  Evangelos Eleftheriou ,  Sedat Oelcer ,  Malcolm Ware

发明人： Gordon DAVIS ,  Jeffrey Derby ,  Evangelos Eleftheriou ,  Sedat Oelcer ,  Malcolm Ware

IPC分类号： H04B1/38

CPC分类号： H04L25/028 ,  H04L27/2626 ,  H04M11/062 ,  Y02D50/44

摘要： A method for operating plurality of DSL modem transmitters integrated within a circuit card. The method includes each DSL modem transmitter: generating a full power physical frame when the DSL modem transmitter is provided with data to transmit; generating a low power physical frame having a control channel signal component and no data; and selecting between the full power physical frame and the low power physical frame for transmission from the DSL modem transmitter, wherein selection of the low power physical frame for transmission from the DSL modem transmitter is based only on the DSL modem transmitter having no data to transmit. The method further includes limiting aggregate flow of data to the plurality of DSL modem transmitters such that a total power required by the plurality of DSL modem transmitters is held below a predefined target power level.

摘要翻译： 一种用于操作集成在电路卡内的多个DSL调制解调器发射机的方法。 该方法包括每个DSL调制解调器发射机：当DSL调制解调器发射机被提供有要传输的数据时，产生全功率物理帧; 生成具有控制信道信号分量且不存在数据的低功率物理帧; 并且在全功率物理帧和低功率物理帧之间选择用于从DSL调制解调器发射机发射，其中，用于从DSL调制解调器发射机传输的低功率物理帧的选择仅基于没有数据传输的DSL调制解调器发射机 。 该方法还包括限制数据到多个DSL调制解调器发射机的汇总流量，使得多个DSL调制解调器发射机所需的总功率保持在预定义的目标功率电平以下。

公开(公告)号：US20080010390A1

公开(公告)日：2008-01-10

申请号：US11856509

申请日：2007-09-17

申请人： Youseff Abdelilah ,  Bartholomew Blaner ,  Gordon Davis ,  Jeffrey Derby ,  Joseph Garvey ,  Malcolm Ware ,  Hua Ye

发明人： Youseff Abdelilah ,  Bartholomew Blaner ,  Gordon Davis ,  Jeffrey Derby ,  Joseph Garvey ,  Malcolm Ware ,  Hua Ye

IPC分类号： G06F3/00

CPC分类号： G06F13/28

摘要： A method, computer program product and system for facilitating inter-digital signal processing (DSP) data communications. A direct memory access (DMA) controller may be configured to facilitate transfers of data between a first and a second DSP processor core coupled to the DMA controller. The DMA controller may read a data structure, referred to as a “buffer descriptor block,” to perform the data transfer. The buffer descriptor block may store both a source address and a destination address indicating where the data is to be retrieved and stored. The buffer descriptor block may further store a value, e.g., number of bytes, indicating a size of the data to be transferred. The DMA controller may then transfer the data located at the source address in the first DSP processor core, with a size, e.g., number of bytes, indicated from the buffer descriptor block, to the destination address in the second DSP processor core.

公开(公告)号：US20080072005A1

公开(公告)日：2008-03-20

申请号：US11944028

申请日：2007-11-21

申请人： Youseff Abdelilah ,  Bartholomew Blaner ,  Gordon Davis ,  Jeffrey Derby ,  Joseph Garvey ,  Malcolm Ware ,  Hua Ye

发明人： Youseff Abdelilah ,  Bartholomew Blaner ,  Gordon Davis ,  Jeffrey Derby ,  Joseph Garvey ,  Malcolm Ware ,  Hua Ye

IPC分类号： G06F12/02

CPC分类号： G06F13/28

摘要： A method, computer program product and system for facilitating inter-digital signal processing (DSP) data communications. A direct memory access (DMA) controller may be configured to facilitate transfers of data between a first and a second DSP processor core coupled to the DMA controller. The DMA controller may read a data structure, referred to as a “buffer descriptor block,” to perform the data transfer. The buffer descriptor block may store both a source address and a destination address indicating where the data is to be retrieved and stored. The buffer descriptor block may further store a value, e.g., number of bytes, indicating a size of the data to be transferred. The DMA controller may then transfer the data located at the source address in the first DSP processor core, with a size, e.g., number of bytes, indicated from the buffer descriptor block, to the destination address in the second DSP processor core.

摘要翻译： 一种用于促进数字间数字信号处理（DSP）数据通信的方法，计算机程序产品和系统。 直接存储器访问（DMA）控制器可以被配置为便于在耦合到DMA控制器的第一和第二DSP处理器核之间传输数据。 DMA控制器可以读取被称为“缓冲器描述符块”的数据结构来执行数据传送。 缓冲器描述符块可以存储指示要检索和存储数据的源地址和目的地址。 缓冲器描述符块还可以存储指示要传送的数据的大小的值，例如字节数。 然后，DMA控制器可以将位于第一DSP处理器核心中的源地址处的数据以从缓冲器描述符块指示的大小（例如，字节数）传送到第二DSP处理器核心中的目的地地址。

公开(公告)号：US20060265576A1

公开(公告)日：2006-11-23

申请号：US11132658

申请日：2005-05-19

申请人： Gordon Davis ,  Jeffrey Derby

发明人： Gordon Davis ,  Jeffrey Derby

IPC分类号： G06F9/44

CPC分类号： G06F9/3017

摘要： In a first aspect, a first processing method is provided. The first processing method includes the steps of (1) operating a processor in a first mode based on an operand size associated with a first instruction received by the processor; and (2) dynamically switching the processor operation mode from the first mode to a second mode based on a different operand size associated with a second instruction received by the processor. Numerous other aspects are provided.

摘要翻译： 在第一方面中，提供了一种第一处理方法。 第一处理方法包括以下步骤：（1）基于与由处理器接收的第一指令相关联的操作数大小，以第一模式操作处理器; 和（2）基于与由处理器接收的第二指令相关联的不同操作数大小，将处理器操作模式从第一模式动态地切换到第二模式。 提供了许多其他方面。

公开(公告)号：US20060265555A1

公开(公告)日：2006-11-23

申请号：US11132656

申请日：2005-05-19

申请人： Gordon Davis ,  Jeffrey Derby

发明人： Gordon Davis ,  Jeffrey Derby

IPC分类号： G06F13/28

CPC分类号： G06F9/3851 ,  G06F9/30112 ,  G06F9/3012 ,  G06F9/384

摘要： In a first aspect, a first method is provided for sharing processor resources. The first method includes the steps of (1) grouping a plurality of physical registers into at least one array, wherein registers in each of the at least one array share read and write ports and wherein at least two types of execution units are coupled to each of the at least one array; and (2) storing different types of data at different times in at least one of the registers from the at least one array, wherein each of the different types of data is associated with at least a different one of the execution units. Numerous other aspects are provided.

摘要翻译： 在第一方面，提供了一种用于共享处理器资源的第一种方法。 第一种方法包括以下步骤：（1）将多个物理寄存器分组成至少一个阵列，其中至少一个阵列中的每一个中的寄存器共享读取和写入端口，并且其中至少两种类型的执行单元耦合到每个 的所述至少一个阵列; 以及（2）在来自所述至少一个阵列的至少一个寄存器中的不同时间存储不同类型的数据，其中所述不同类型的数据中的每一个与至少一个所述执行单元相关联。 提供了许多其他方面。

公开(公告)号：US20060039457A1

公开(公告)日：2006-02-23

申请号：US11237001

申请日：2005-09-28

申请人： Gordon Davis ,  Jeffrey Derby ,  Evangelos Eleftheriou ,  Sedat Oelcer ,  Malcolm Ware

发明人： Gordon Davis ,  Jeffrey Derby ,  Evangelos Eleftheriou ,  Sedat Oelcer ,  Malcolm Ware

IPC分类号： H04B1/38

CPC分类号： H04L25/028 ,  H04L27/2626 ,  H04M11/062 ,  Y02D50/44

摘要： A low power DSL modem transmitter, suitable for incorporation in integrated DSLAM server line cards, transmits full power physical frames which include a control channel and a data field when data is available for transmission and physical frames having only a control channel or a control channel and a low power synchronization field when data is not available for transmission. And a method for controlling the total power dissipated in the integrated DSLAM by selectively restricting the flow of data packets to the DSLs.

公开(公告)号：US20050188129A1

公开(公告)日：2005-08-25

申请号：US10783757

申请日：2004-02-20

申请人： Youseff Abdelilah ,  Bartholomew Blaner ,  Gordon Davis ,  Jeffrey Derby ,  Joseph Garvey ,  Malcolm Ware ,  Hua Ye

发明人： Youseff Abdelilah ,  Bartholomew Blaner ,  Gordon Davis ,  Jeffrey Derby ,  Joseph Garvey ,  Malcolm Ware ,  Hua Ye

IPC分类号： G06F3/00 ,  G06F13/28 ,  H04L29/06

CPC分类号： G06F13/28

摘要： A method, computer program product and system for facilitating inter-digital signal processing (DSP) data communications. A direct memory access (DMA) controller may be configured to facilitate transfers of data between a first and a second DSP processor core coupled to the DMA controller. The DMA controller may read a data structure, referred to as a “buffer descriptor block,” to perform the data transfer. The buffer descriptor block may store both a source address and a destination address indicating where the data is to be retrieved and stored. The buffer descriptor block may further store a value, e.g., number of bytes, indicating a size of the data to be transferred. The DMA controller may then transfer the data located at the source address in the first DSP processor core, with a size, e.g., number of bytes, indicated from the buffer descriptor block, to the destination address in the second DSP processor core.

摘要翻译： 一种用于促进数字间数字信号处理（DSP）数据通信的方法，计算机程序产品和系统。 直接存储器访问（DMA）控制器可以被配置为便于在耦合到DMA控制器的第一和第二DSP处理器核之间传输数据。 DMA控制器可以读取被称为“缓冲器描述符块”的数据结构来执行数据传送。 缓冲器描述符块可以存储指示要检索和存储数据的源地址和目的地址。 缓冲器描述符块还可以存储指示要传送的数据的大小的值，例如字节数。 然后，DMA控制器可以将位于第一DSP处理器核心中的源地址处的数据以从缓冲器描述符块指示的大小（例如，字节数）传送到第二DSP处理器核心中的目的地地址。

公开(公告)号：US20070226466A1

公开(公告)日：2007-09-27

申请号：US11366884

申请日：2006-03-02

申请人： Peter Capek ,  Jeffrey Derby ,  Robert Montoye

发明人： Peter Capek ,  Jeffrey Derby ,  Robert Montoye

IPC分类号： G06F9/30

CPC分类号： G06F9/3012 ,  G06F9/3004 ,  G06F9/30098 ,  G06F9/3013 ,  G06F9/30138 ,  G06F9/30145 ,  G06F9/30167 ,  G06F9/35 ,  G06F9/384

摘要： A facility is provided for managing register maps for map-based indirect register file access within a processor. The management facility includes a register mapping including a set of maps, each map of the set of maps having a plurality of map registers. A set of actual registers is indirectly accessed by the processor via map entries of the set of maps. The number of actual registers in the set of actual registers is greater than the number of map entries in the set of maps, and the map entries of the set of maps reference only a subset of the set of actual registers at any given time. The facility includes managing updates to multiple entries of the set of maps of the register mapping by updating multiple map entries of at least one map of the set of maps responsive to executing a single update instruction.

摘要翻译： 提供了一种用于管理处理器内基于地图的间接寄存器文件访问的寄存器映射的设施。 管理设施包括包括一组映射的寄存器映射，该映射集合的每个映射具有多个映射寄存器。 一组实际寄存器由处理器通过地图集的映射条目间接访问。 实际寄存器组中实际寄存器的数量大于映射集中映射条目的数量，映射集合的映射条目仅引用任何给定时间的实际寄存器集合的子集。 该设施包括通过基于执行单个更新指令来更新该组映射的至少一个映射的多个映射条目来管理对该映射映射集合的多个条目的更新。