公开(公告)号：US11385709B2

公开(公告)日：2022-07-12

申请号：US17233344

申请日：2021-04-16

申请人： GOWIN Semiconductor Corporation, Ltd.

发明人： Jinghui Zhu

IPC分类号： G06F1/26 ,  G06F1/32 ,  G06F1/3296 ,  G06F30/34 ,  G06F1/3246 ,  G06F1/3234

摘要： A programmable semiconductor integrated circuit fabricated on a single microchip device capable of being selectively programmed to perform one or more logic functions provides a sleep mode using an intermittent power saving logic. The circuit includes configurable logic blocks (“LB”), memory, switch, and sleep controller. While LB can enter a power saving sleep mode (“PSSM”) in accordance with its power supply, the memory stores the configuration information for the LB. The switch is configured to manage the LB power supply based on a configurable sleep signal for facilitating the PSSM. The sleep controller facilitates generation of the configurable sleep signal in response to the signal from a power saving output port associated with the LB.

公开(公告)号：US10990556B2

公开(公告)日：2021-04-27

申请号：US14831204

申请日：2015-08-20

申请人： Gowin Semiconductor Corporation, Ltd.

发明人： Jinghui Zhu ,  San-Ta Kow

IPC分类号： G06F13/40 ,  G06F13/10 ,  G06F13/16 ,  G06F9/445 ,  G06F15/78 ,  G06F9/4401

摘要： The present invention discloses a programmable logic device with on-chip user non-volatile memory, comprising: a programmable logic array, which is a user programmable logic array and comprises a SRAM array and a logic block array with an interface; the SRAM array is used to store configuration data to control the logic block array in real time, therefore, the logic block can be formed to perform the function a user desires; a non-volatile memory block, comprising one or more segments storing configuration data and one or more segments storing user data which is used during FPGA's normal operation after configuration; the non-volatile memory block has only one interface, and the non-volatile memory block connects to a programming controller through the interface; a programming controller, which can randomly access the non-volatile memory through a data bus, an address bus, and corresponding control signals.

公开(公告)号：US20220294451A1

公开(公告)日：2022-09-15

申请号：US17828037

申请日：2022-05-31

申请人： GOWIN Semiconductor Corporation, Ltd.

发明人： Grant Thomas Jennings ,  Jinghui Zhu

IPC分类号： H03K19/17736 ,  H03K19/17728

摘要： An integrated circuit (“IC”) module includes a substrate, multiple field-programmable gate array (“FPGA”) dies, and pads capable of being selectively configured to perform one or more user defined logic functions. The substrate is configured to house multiple FPGA dies side-by-side in an array formation facilitating transmission of signals between the FPGA dies or chips. The FPGA dies are placed on the substrate functioning as a single FPGA device. The periphery dies of the FPGA dies are configured for external connectivity and the interior dies which are interconnected to perform user defined logic functions. The pads, in one aspect, coupling to the FPGA dies, are configured to provide connections between at least some of the FPGA dies.

公开(公告)号：US11368156B2

公开(公告)日：2022-06-21

申请号：US17334985

申请日：2021-05-31

申请人： GOWIN Semiconductor Corporation, Ltd.

发明人： Grant Thomas Jennings ,  Jinghui Zhu

IPC分类号： H03K19/17736 ,  H03K19/17728

摘要： An integrated circuit (“IC”) module includes a substrate, multiple field-programmable gate array (“FPGA”) dies, and pads capable of being selectively configured to perform one or more user defined logic functions. The substrate is configured to house multiple FPGA dies side-by-side in an array formation facilitating transmission of signals between the FPGA dies or chips. The FPGA dies are placed on the substrate functioning as a single FPGA device. The periphery dies of the FPGA dies are configured for external connectivity and the interior dies which are interconnected to perform user defined logic functions. The pads, in one aspect, coupling to the FPGA dies, are configured to provide connections between at least some of the FPGA dies.

公开(公告)号：US20210232209A1

公开(公告)日：2021-07-29

申请号：US17233344

申请日：2021-04-16

申请人： GOWIN Semiconductor Corporation, Ltd.

发明人： Jinghui Zhu

IPC分类号： G06F1/3296 ,  G06F30/34 ,  G06F1/3246 ,  G06F1/3234

摘要： A programmable semiconductor integrated circuit fabricated on a single microchip device capable of being selectively programmed to perform one or more logic functions provides a sleep mode using an intermittent power saving logic. The circuit includes configurable logic blocks (“LB”), memory, switch, and sleep controller. While LB can enter a power saving sleep mode (“PSSM”) in accordance with its power supply, the memory stores the configuration information for the LB. The switch is configured to manage the LB power supply based on a configurable sleep signal for facilitating the PSSM. The sleep controller facilitates generation of the configurable sleep signal in response to the signal from a power saving output port associated with the LB.

公开(公告)号：US10997088B2

公开(公告)日：2021-05-04

申请号：US15633172

申请日：2017-06-26

申请人： Gowin Semiconductor Corporation, Ltd

发明人： San-Ta Kow ,  Jinghui Zhu ,  Diwakar Chopperla

IPC分类号： G06F21/00 ,  G06F12/14 ,  G06F3/06

摘要： A secrecy system and a decryption method of on-chip data stream of nonvolatile FPGA are provided in the present invention. The nonvolatile memory module of the system is configured to only allow the full erase operation. After the full erase operation is finished, the nonvolatile memory module gets into the initial state. Only the operation to the nonvolatile memory module under the initial state is effective, and thereby the encryption region unit is arranged in the nonvolatile memory module. Only the decryption data written into the encryption region unit under the initial state can make the nonvolatile memory module to be readable, so that the decryption of the system is finished, which greatly improves the secrecy precision.

公开(公告)号：US20180011803A1

公开(公告)日：2018-01-11

申请号：US15633172

申请日：2017-06-26

申请人： Gowin Semiconductor Corporation, Ltd

发明人： San-Ta Kow ,  Jinghui Zhu ,  Diwakar Chopperla

IPC分类号： G06F12/14 ,  G06F3/06

CPC分类号： G06F12/1408 ,  G06F3/0619 ,  G06F3/062 ,  G06F3/0623 ,  G06F3/0652 ,  G06F3/0679 ,  G06F3/0688

摘要： A secrecy system and a decryption method of on-chip data stream of nonvolatile FPGA are provided in the present invention. The nonvolatile memory module of the system is configured to only allow the full erase operation. After the full erase operation is finished, the nonvolatile memory module gets into the initial state. Only the operation to the nonvolatile memory module under the initial state is effective, and thereby the encryption region unit is arranged in the nonvolatile memory module. Only the decryption data written into the encryption region unit under the initial state can make the nonvolatile memory module to be readable, so that the decryption of the system is finished, which greatly improves the secrecy precision.

公开(公告)号：US20230014412A1

公开(公告)日：2023-01-19

申请号：US17953317

申请日：2022-09-26

申请人： GOWIN Semiconductor Corporation, Ltd.

发明人： Jinghui Zhu ,  Diwakar Chopperla

IPC分类号： G06F30/347

摘要： A programmable semiconductor system includes a programmable integrated circuit (“PIC”) and storage capable of facilitating a multi-boot with backup default configuration (“MBC”) process. The PIC, in one embodiment, includes a dual-mode port (“DMP”), configurable logic blocks (“LBs”), routing connections, and a configuration memory for providing configuration data to facilitate user-defined logic functions. The DMP, in one aspect, is operable to handle the configuration data during a configuration mode. Alternatively, the DMP is operable to handle the user data during a logic operation mode. In one aspect, the user configuration data contains the address of the second memory containing DCD.

公开(公告)号：US20210376833A1

公开(公告)日：2021-12-02

申请号：US17334985

申请日：2021-05-31

申请人： GOWIN Semiconductor Corporation, Ltd.

发明人： Grant Thomas Jennings ,  Jinghui Zhu

IPC分类号： H03K19/17736 ,  H03K19/17728

摘要： An integrated circuit (“IC”) module includes a substrate, multiple field-programmable gate array (“FPGA”) dies, and pads capable of being selectively configured to perform one or more user defined logic functions. The substrate is configured to house multiple FPGA dies side-by-side in an array formation facilitating transmission of signals between the FPGA dies or chips. The FPGA dies are placed on the substrate functioning as a single FPGA device. The periphery dies of the FPGA dies are configured for external connectivity and the interior dies which are interconnected to perform user defined logic functions. The pads, in one aspect, coupling to the FPGA dies, are configured to provide connections between at least some of the FPGA dies.

公开(公告)号：US10003339B1

公开(公告)日：2018-06-19

申请号：US15786625

申请日：2017-10-18

申请人： GUANGDONG GOWIN SEMICONDUCTOR CORPORATION, LTD.

发明人： Jinghui Zhu ,  Bin Gao ,  Chienkuang Chen

IPC分类号： H03K19/0185 ,  H03K17/22 ,  H03K19/177

CPC分类号： H03K19/018507 ,  H03K17/223 ,  H03K19/177

摘要： A GPIO interface circuit compatible with output of MIPI signals, comprises a first CMOS signal output module (10), an LVDS signal output module (30), a second CMOS signal output module (20). When an MIPI output enable input of the LVDS signal output module (30) is enabled and output enable inputs of the first and second CMOS signal output modules (10, 20) are both disabled, a first and second pull-down modules (40, 50) are in active state accordingly, and the LVDS signal output module (30) outputs a current signal to the first or second pull-down module (40, 50) to ensure voltage of the first or second signal output be a preset voltage, which can achieve MIPI HS Mode output.