公开(公告)号：US07267008B2

公开(公告)日：2007-09-11

申请号：US11046259

申请日：2005-01-28

申请人： Grant A. Gordon ,  Nicholas Wilt

发明人： Grant A. Gordon ,  Nicholas Wilt

IPC分类号： G01N29/12 ,  G01N29/14 ,  G01N1/00

CPC分类号： G01N29/343 ,  G01N29/041 ,  G01N29/36 ,  G01N2291/0427 ,  G01N2291/101 ,  G01N2291/2694

摘要： A transducer for use in a structural health monitoring system includes a single transducer element. The transducer includes a transmit assembly coupled to the single transducer element. This assembly is configured to produce a multi-cycle square wave drive signal for stimulating the transducer. Additionally, a transmit/receive switch coupled to the single transducer element is provided. This assembly is configured to isolate the drive signal from the receive assembly used to sense the electrical signal generated from any received elastic waves.

摘要翻译： 用于结构健康监测系统的换能器包括单个换能器元件。 换能器包括耦合到单个换能器元件的发射组件。 该组件被配置为产生用于刺激换能器的多周期方波驱动信号。 另外，提供耦合到单个换能器元件的发射/接收开关。 该组件被配置为将来自用于感测从任何接收的弹性波产生的电信号的接收组件的驱动信号隔离开。

公开(公告)号：US20120068733A1

公开(公告)日：2012-03-22

申请号：US12886276

申请日：2010-09-20

申请人： Mitch Fletcher ,  Thom Kreider ,  Nicholas Wilt

发明人： Mitch Fletcher ,  Thom Kreider ,  Nicholas Wilt

IPC分类号： H03K19/177

CPC分类号： H03K19/177

摘要： Methods and apparatus are provided for a Universal functionality Module (UFM). The apparatus comprises a programmable logic device (PLD) configured to be reprogrammed in real time and a means for universally interfacing the PLD with any effectuator device. The UFM loads a startup personality bit stream from a boot memory, which allows it to read a pin configuration associated with a effectuator device. The UFM receives a function personality associated with the pin configuration, writes the function personality to programmable logic device, and initiates the function personality.

摘要翻译： 为通用功能模块（UFM）提供了方法和装置。 该装置包括被配置为实时重新编程的可编程逻辑器件（PLD）和用于将PLD与任何实现器件通用接口的装置。 UFM从启动存储器加载启动个性位流，这允许它读取与实现器设备相关联的引脚配置。 UFM接收与引脚配置相关的功能个性，将功能个性写入可编程逻辑器件，并启动功能个性。

公开(公告)号：US20120030519A1

公开(公告)日：2012-02-02

申请号：US12847687

申请日：2010-07-30

申请人： Nicholas Wilt ,  Scott Gray

发明人： Nicholas Wilt ,  Scott Gray

IPC分类号： G06F11/30 ,  G06F9/40

CPC分类号： G06F11/1645 ,  G06F11/1637

摘要： A self-checking network is provided, comprising a first command processor configured to execute a performance function and a second command processor configured to execute the performance function, coupled to the first command processor. The self-checking network also comprises a first monitor processor configured to execute a monitor function that is coupled to the first command processor and a second monitor processor configured to execute the monitor function that is coupled to the second command processor. The first and second command processors compare outputs, the first and second monitor processors compare outputs, and the first monitor processor determines whether an output of the first command processor exceeds a first selected limit.

摘要翻译： 提供了一种自检网络，包括被配置为执行演奏功能的第一命令处理器和被配置为执行与第一命令处理器耦合的演奏功能的第二命令处理器。 自检网络还包括被配置为执行耦合到第一命令处理器的监视功能的第一监视器处理器和被配置为执行耦合到第二命令处理器的监视功能的第二监视器处理器。 第一和第二命令处理器比较输出，第一和第二监视器处理器比较输出，并且第一监视器处理器确定第一命令处理器的输出是否超过第一选择的限制。

公开(公告)号：US20110214043A1

公开(公告)日：2011-09-01

申请号：US12713712

申请日：2010-02-26

申请人： Nicholas Wilt ,  Scott Gray ,  Mitch Fletcher

发明人： Nicholas Wilt ,  Scott Gray ,  Mitch Fletcher

IPC分类号： G06F11/07

CPC分类号： G06F11/1645 ,  G06F11/1625 ,  H04L1/244

摘要： Methods and apparatus are provided for verifying the integrity of a signal transmitted across a multiple rail data bus. The method and apparatus provide for independently processing a signal by a first processor and a second processor, the first and second processors being connected in parallel thereby generating a first processed signal and a second processed signal. Each of the processed signals is split into a first component sequence and a second component sequence, the first component sequences being different from the second component sequences. It is then determined that the first component sequences are not identical and that the second component sequences are not identical. If either of the first component sequences is not identical, or if either of the second component sequences is not identical, then an error signal is transmitted to a receiving device via a first or second rail of the bus.

摘要翻译： 提供了用于验证跨多轨数据总线传输的信号的完整性的方法和装置。 该方法和装置提供由第一处理器和第二处理器独立地处理信号，第一和第二处理器并联连接，从而产生第一处理信号和第二处理信号。 每个经处理的信号被分成第一组分序列和第二组分序列，第一组分序列不同于第二组分序列。 然后确定第一组分序列不相同，并且第二组分序列不相同。 如果第一分量序列中的任一个不相同，或者如果第二分量序列中的任一个不相同，则通过总线的第一或第二轨道向接收设备发送错误信号。

公开(公告)号：US20070136730A1

公开(公告)日：2007-06-14

申请号：US11670226

申请日：2007-02-01

申请人： Nicholas Wilt ,  Sameer Nene ,  Joseph Beda

发明人： Nicholas Wilt ,  Sameer Nene ,  Joseph Beda

IPC分类号： G06F9/46

CPC分类号： G06F9/4843 ,  G06F9/3851 ,  G06F9/3879

摘要： Systems and methods are provided for managing the computational resources of coprocessor(s), such as graphics processor(s), in a computing system. The systems and methods illustrate management of computational resources of coprocessors to facilitate efficient execution of multiple applications in a multitasking environment. By enabling multiple threads of execution to compose command buffers in parallel, submitting those command buffers for scheduling and dispatch by the operating system, and fielding interrupts that notify of completion of command buffers, the system enables multiple applications to efficiently share the computational resources available in the system.

摘要翻译： 提供了系统和方法来管理计算系统中的协处理器（诸如图形处理器）的计算资源。 系统和方法说明了协处理器的计算资源的管理，以便于在多任务环境中有效执行多个应用程序。 通过使多个执行线程并行组成命令缓冲区，提交由操作系统调度和分派的那些命令缓冲区，以及通知命令缓冲区完成的中断，系统使多个应用程序能够有效地共享可用的计算资源 系统。

公开(公告)号：US20050168481A1

公开(公告)日：2005-08-04

申请号：US11093636

申请日：2005-03-29

申请人： Nicholas Wilt ,  Gideon Yuval ,  Michael Stokes

发明人： Nicholas Wilt ,  Gideon Yuval ,  Michael Stokes

IPC分类号： H04N1/60 ,  G09G5/02

CPC分类号： H04N1/6016

摘要： An imaging or other sensory reproduction system efficiently converts image or other sensory data between a perceptual color space (e.g., the sRGB color space) and a physical color space (unity gamma) or other perceptual/physical sensory models that are related by an expression involving a computationally expensive exponential function. The imaging system calculates exponential functions that can be composed from computationally inexpensive operations, such as square root, square, reciprocal, as well as multiplications and/or additions and subtractions. These computationally less expensive functions are then combined, such as in a weighted and/or offset mean, summation or difference to approximate the computationally expensive exponential function. The imaging system evaluates the expression using the approximation to efficiently yield the converted image data. The efficient conversion between perceptual and physical color spaces allows operations, such as blending and anti-aliasing, to be performed in the physical color space before display of a perceptual color space image.

公开(公告)号：US20050083339A1

公开(公告)日：2005-04-21

申请号：US10970261

申请日：2004-10-21

申请人： Nicholas Wilt ,  Colin McCartney

发明人： Nicholas Wilt ,  Colin McCartney

IPC分类号： G06T13/00 ,  G06F15/00 ,  G06T11/00 ,  G09G5/00 ,  G09G5/14 ,  G09G5/393 ,  G09G5/399 ,  G06F13/00 ,  G06T15/00

CPC分类号： G09G5/14 ,  G09G5/393 ,  G09G5/397 ,  G09G5/399 ,  G09G2320/103 ,  G09G2340/0407 ,  G09G2340/10 ,  G09G2340/12 ,  G09G2340/125

摘要： Disclosed are methods and systems for interfaces between video applications and display screens that allow applications to intelligently use display resources of their host device without tying themselves too closely to operational particulars of that host. A graphics arbiter provides display environment information to the video applications and accesses the applications' output to efficiently present that output to the display screen, possibly transforming the output or allowing another application to transform it in the process. The graphics arbiter tells applications the estimated time when the next frame will be displayed on the screen. Applications tailor their output to the estimated display time, thus improving output quality while decreasing resource waste by avoiding the production of “extra” frames. The graphics arbiter tells an application when its output is fully or partially occluded so that the application need not expend resources to draw portions of frames that are not visible.

摘要翻译： 公开了用于视频应用和显示屏幕之间的接口的方法和系统，其允许应用程序智能地使用其主机设备的显示资源，而不会太贴近该主机的操作细节。 图形仲裁器向视频应用程序提供显示环境信息，并访问应用程序的输出以有效地将该输出提供给显示屏幕，可能转换输出或允许另一应用程序在此过程中转换它。 图形仲裁器告诉应用程序在屏幕上显示下一帧的估计时间。 应用程序将其输出定制到估计的显示时间，从而通过避免产生“额外”帧来提高输出质量，同时减少资源浪费。 图形仲裁器告诉应用程序，当其输出完全或部分闭塞时，应用程序不需要花费资源来绘制不可见框架的部分。

公开(公告)号：US08390324B2

公开(公告)日：2013-03-05

申请号：US12886276

申请日：2010-09-20

申请人： Mitch Fletcher ,  Thom Kreider ,  Nicholas Wilt

发明人： Mitch Fletcher ,  Thom Kreider ,  Nicholas Wilt

IPC分类号： H03K19/177

CPC分类号： H03K19/177

摘要： Methods and apparatus are provided for a Universal functionality Module (UFM). The apparatus comprises a programmable logic device (PLD) configured to be reprogrammed in real time and a means for universally interfacing the PLD with any effectuator device. The UFM loads a startup personality bit stream from a boot memory, which allows it to read a pin configuration associated with a effectuator device. The UFM receives a function personality associated with the pin configuration, writes the function personality to programmable logic device, and initiates the function personality.

摘要翻译： 为通用功能模块（UFM）提供了方法和装置。 该装置包括被配置为实时重新编程的可编程逻辑器件（PLD）和用于将PLD与任何实现器件通用接口的装置。 UFM从启动存储器加载启动个性位流，这允许它读取与实现器设备相关联的引脚配置。 UFM接收与引脚配置相关的功能个性，将功能个性写入可编程逻辑器件，并启动功能个性。

公开(公告)号：US08316192B2

公开(公告)日：2012-11-20

申请号：US12575709

申请日：2009-10-08

申请人： Scott Gray ,  Nicholas Wilt

发明人： Scott Gray ,  Nicholas Wilt

IPC分类号： G06F12/00

CPC分类号： G11C8/16 ,  G06F13/1684

摘要： Systems and methods for improved multiple-port memory are provided. In one embodiment, a processing system comprises: at least one processing core; a peripheral bus; and a memory for storing digital data, the memory divided into a first and a second partition of memory segments. The memory includes a first port coupled to the peripheral bus providing read access and write access only to the first partition, wherein the first partition stores peripheral data associated with one or more peripheral components coupled to the peripheral bus; a second port coupled to the at least one processor providing read-only access to only the second partition, wherein the second partition stores executable code for the at least one processing core; and a third port coupled to the at least one processor providing read access and write access to the entire first partition and the second partition.

摘要翻译： 提供了改进多端口存储器的系统和方法。 在一个实施例中，处理系统包括：至少一个处理核心; 外围总线 以及用于存储数字数据的存储器，所述存储器被分成存储器段的第一和第二分区。 存储器包括耦合到外围总线的第一端口，仅提供对第一分区的读访问和写访问，其中第一分区存储与耦合到外围总线的一个或多个外围组件相关联的外围数据; 耦合到所述至少一个处理器的第二端口，其提供仅对所述第二分区的只读访问，其中所述第二分区存储用于所述至少一个处理核心的可执行代码; 以及耦合到所述至少一个处理器的第三端口，其提供对所述整个第一分区和所述第二分区的读访问和写访问。

公开(公告)号：US08010846B1

公开(公告)日：2011-08-30

申请号：US12419153

申请日：2009-04-06

申请人： Byron Birkedahl ,  Nicholas Wilt ,  Art McCready ,  Brendan Hall ,  Aaron Larson

发明人： Byron Birkedahl ,  Nicholas Wilt ,  Art McCready ,  Brendan Hall ,  Aaron Larson

IPC分类号： G06F11/00 ,  G06F11/14

CPC分类号： G06F9/4881 ,  G06F11/1645 ,  G06F11/1687

摘要： Methods and systems for a scalable self-checking processing platform are described herein. According to one embodiment, during an execution frame, a first processing element executes both a high-criticality application and a first low-criticality application. During that same execution frame, a second processing element executes both the high-criticality application and a second low-criticality application. The high-criticality application output from the first processing element is compared with that from the second processing element before the next execution frame, and a fault occurs when the output does not match. The low-criticality application is not duplicated or compared. This and other embodiments allow high-criticality applications to be appropriated checked while avoiding the over-dedication of resources to low-criticality applications that do not warrant self-checking.

摘要翻译： 本文描述了可扩展自检处理平台的方法和系统。 根据一个实施例，在执行帧期间，第一处理元件执行高关键性应用和第一低关键性应用。 在该相同的执行帧期间，第二处理元件执行高关键性应用和第二低关键性应用。 从第一处理元件输出的高关键性应用与下一个执行帧之前的第二处理元件进行比较，当输出不匹配时发生故障。 低重要性应用程序不重复或比较。 这个和其他实施例允许高密度性应用被检查，同时避免资源过度投入到不保证自我检查的低关键性应用中。