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    Seralized race-free virtual barrier network
    1.
    发明授权
    Seralized race-free virtual barrier network 失效
    无线化的无竞争虚拟屏障网络

    公开(公告)号：US6085303A

    公开(公告)日：2000-07-04

    申请号：US972010

    申请日：1997-11-17

    申请人： Greg Thorson ,  Randal S. Passint ,  Steven L. Scott

    发明人： Greg Thorson ,  Randal S. Passint ,  Steven L. Scott

    IPC分类号： G06F9/46 ,  G06F15/16

    CPC分类号： G06F9/52

    摘要： Improved method and apparatus for facilitating barrier and eureka synchronization in a massively parallel processing system. The present barrier/eureka synchronization mechanism provides a partitionable, low-latency, immediately reusable, robust mechanism which can operate on a physical data-communications network and can be used to alert all processor entities (PEs) in a partition when all of the PEs in that partition have reached a designated barrier point in their individual program code, or when any one of the PEs in that partition has reached a designated eureka point in its individual program code, or when either the barrier or eureka requirements have been satisfied, which ever comes first. Multiple overlapping synchronization partitions are available simultaneously through the use of a plurality of parallel synchronization contexts. The present synchronization mechanism may be implemented on either a dedicated barrier network, or superimposed as a virtual barrier/eureka network operating on a physical data-communications network which is also used for data interchange, operating system functions, and other purposes. The present barrier/eureka mechanism also supports zero to N processor entities at each router node ("leaves" on the barrier tree), and provides a barrier sequence counter for each barrier context in order to resolve potential race conflicts that might otherwise arise.

    摘要翻译： 改进的方法和装置，用于在大规模并行处理系统中促进障碍和尤里卡同步。 当前的屏障/尤里卡同步机制提供了一种可分割的，低延迟的，立即可重用的鲁棒机制，其可以在物理数据通信网络上操作，并且可以用于警告所有PE中的所有处理器实体（PE） 在该分区已经到达其个别程序代码中的指定障碍点，或者当该分区中的任何一个PE在其各个程序代码中已经达到指定的尤里卡点时，或者当满足屏障或尤里卡要求时，哪个 曾经来过 多个重叠的同步分区可以通过使用多个并行同步上下文同时获得。 本同步机制可以在专用屏障网络上实现，或者叠加在用于数据交换，操作系统功能和其他目的的物理数据通信网络上操作的虚拟屏障/尤里卡网络。 当前的屏障/尤里卡机制还支持每个路由器节点处的零到N个处理器实体（“阻挡树”上的“离开”），并且为每个屏障上下文提供屏障序列计数器，以便解决否则可能出现的潜在的竞争冲突。

    Hybrid hypercube/torus architecture
    2.
    发明授权
    Hybrid hypercube/torus architecture 失效
    混合超立方体/环面架构

    公开(公告)号：US06230252B1

    公开(公告)日：2001-05-08

    申请号：US08971588

    申请日：1997-11-17

    申请人： Randal S. Passint ,  Greg Thorson ,  Michael B. Galles

    发明人： Randal S. Passint ,  Greg Thorson ,  Michael B. Galles

    IPC分类号： G06F1300

    CPC分类号： G06F15/17381 ,  G06F15/803

    摘要： A scalable multiprocessor system includes processing element nodes. A scalable interconnect network includes physical communication links interconnecting the processing element nodes in an n-dimensional topology, and routers for routing messages between the processing element nodes on the physical communication links. The routers are capable of routing messages in hypercube topologies of at least up to six dimensions, and further capable of routing messages in at least one n dimensional torus topology having at least one of the n dimensions having a radix greater than four, such as a 4×8×4 torus topology.

    摘要翻译： 可扩展的多处理器系统包括处理元件节点。 可扩展互连网络包括将n维拓扑中的处理元件节点互连的物理通信链路和用于在物理通信链路上的处理元件节点之间路由消息的路由器。 路由器能够在至少六个维度的超立方体拓扑中路由消息，并且还能够在至少一个n维环面拓扑中路由消息，其中n维的至少一个具有大于4的基数，诸如 4x8x4环形拓扑。

    Virtual channel assignment in large torus systems
    5.
    发明授权
    Virtual channel assignment in large torus systems 失效
    大环面系统中的虚拟通道分配

    公开(公告)号：US6101181A

    公开(公告)日：2000-08-08

    申请号：US971591

    申请日：1997-11-17

    申请人： Randal S. Passint ,  Greg Thorson ,  Michael B. Galles

    发明人： Randal S. Passint ,  Greg Thorson ,  Michael B. Galles

    IPC分类号： G06F15/173 ,  H04L12/56

    CPC分类号： G06F15/17381

    摘要： A multiprocessor computer system includes processing element nodes interconnected by physical communication links. Routers route messages between processing element nodes on the physical communication links. Each router includes input ports for receiving messages, output ports for sending messages from the router, two types of virtual channels, a lookup table associated with the input port having a lookup table virtual channel number, and a virtual channel assignment mechanism. The virtual channel assignment mechanism assigns an output next virtual channel number for determining the type of virtual channel to be used for routing from a next router along a given route. The next virtual channel number is assigned based on the lookup table virtual channel number and an input next virtual channel number received from a previous router along the given route.

    摘要翻译： 多处理器计算机系统包括通过物理通信链路互连的处理单元节点。 路由器在物理通信链路上的处理单元节点之间路由消息。 每个路由器包括用于接收消息的输入端口，用于从路由器发送消息的输出端口，两种类型的虚拟信道，与具有查找表虚拟信道号的输入端口相关联的查找表，以及虚拟信道分配机制。 虚拟信道分配机制为下一个虚拟信道号分配输出，用于确定用于沿着给定路由从下一个路由器进行路由的虚拟信道的类型。 基于查找表虚拟通道号和沿着给定路线从先前的路由器接收的输入的下一个虚拟通道号来分配下一个虚拟通道号。

    Router table lookup mechanism
    6.
    发明授权
    Router table lookup mechanism 失效
    路由器表查找机制

    公开(公告)号：US5970232A

    公开(公告)日：1999-10-19

    申请号：US971587

    申请日：1997-11-17

    申请人： Randal S. Passint ,  Michael B. Galles ,  Greg Thorson

    发明人： Randal S. Passint ,  Michael B. Galles ,  Greg Thorson

    IPC分类号： G06F15/173 ,  G06F13/00 ,  H04L12/54

    CPC分类号： G06F15/17381

    摘要： A multiprocessor computer system includes processing element nodes interconnected by physical communication links in a n-dimensional topology, which includes at least two global partitions. Routers route messages between processing element nodes and include ports for receiving and sending messages, and lookup tables having a local router table having directions for routing between processor element nodes within a global partition, and a global router table having directions for routing between processor element nodes located in different global partitions. The directions from the local table are selected for routing from the next router along a given route if the current processing element node is in a destination global partition or if the current processing element node is one plus or minus hop from reaching the destination global partition and the route is exiting on a port that routes to the destination global partition, else the directions from the global router table are selected for routing from the next router.

    摘要翻译： 多处理器计算机系统包括通过n维拓扑中的物理通信链路互连的处理元件节点，其包括至少两个全局分区。 路由器在处理元件节点之间路由消息并且包括用于接收和发送消息的端口，以及具有本地路由器表的查找表，该表具有在全局分区内的处理器元件节点之间路由的指示，以及具有用于在处理器元件节点之间路由的方向的全局路由器表 位于不同的全局分区。 如果当前处理元素节点在目的地全局分区中，或者当前处理元素节点是否到达目的地全局分区为一个加号或者多跳，则选择来自本地表的方向用于沿着给定路由从下一个路由器路由， 该路由正在路由到目的地全局分区的端口上退出，否则选择来自全局路由器表的方向用于从下一个路由器路由。

    Multiprocessor computer system and method for maintaining cache coherence utilizing a multi-dimensional cache coherence directory structure
    8.
    发明授权
    Multiprocessor computer system and method for maintaining cache coherence utilizing a multi-dimensional cache coherence directory structure 失效
    多处理器计算机系统和使用多维高速缓存一致性目录结构来维持高速缓存一致性的方法

    公开(公告)号：US06633958B1

    公开(公告)日：2003-10-14

    申请号：US08971184

    申请日：1997-11-17

    申请人： Randal S. Passint ,  Steven L. Scott

    发明人： Randal S. Passint ,  Steven L. Scott

    IPC分类号： G06F1300

    CPC分类号： G06F12/0826

    摘要： A cache coherence system and method for use in a multiprocessor computer system having a plurality of processor nodes, a memory and an interconnect network connecting the plurality of processor nodes to the memory. Each processor node includes one or more processors. The memory includes a plurality of lines and a cache coherence directory structure having a plurality of directory structure entries. Each of the directory structure entries is associated with one of the plurality of lines and each directory structure entry includes processor pointer information, expressed as a set of bit vectors, indicating the processors that have cached copies of lines in memory. Processor pointer information may be a function of a processor number assigned to each processor; the processor number may be expressed as a function of a first set of bits and a second set of bits which are respectively mapped into first and second bit vectors of the n bit vectors.

    摘要翻译： 一种在具有多个处理器节点的多处理器计算机系统中使用的高速缓存一致性系统和方法，将多个处理器节点连接到存储器的存储器和互连网络。 每个处理器节点包括一个或多个处理器。 存储器包括具有多个目录结构条目的多行和高速缓存一致性目录结构。 目录结构条目中的每一个都与多个行中的一个相关联，并且每个目录结构条目包括表示为一组位向量的处理器指针信息，指示具有存储器中的行的缓存副本的处理器。 处理器指针信息可以是分配给每个处理器的处理器号的函数; 处理器号可以表示为分别映射到n位向量的第一和第二位向量中的第一组位和第二组位的函数。

    Node Synchronization for Multi-Processor Computer Systems
    9.
    发明申请
    Node Synchronization for Multi-Processor Computer Systems 审中-公开
    多处理器计算机系统的节点同步

    公开(公告)号：US20090259696A1

    公开(公告)日：2009-10-15

    申请号：US12330413

    申请日：2008-12-08

    申请人： John Carter ,  Randal S. Passint ,  Donglai Dai ,  Zhen Fang ,  Lixin Zhang ,  Gregory M. Thorson

    发明人： John Carter ,  Randal S. Passint ,  Donglai Dai ,  Zhen Fang ,  Lixin Zhang ,  Gregory M. Thorson

    IPC分类号： G06F17/30

    CPC分类号： G06F15/16 ,  Y10S707/99952

    摘要： A method and apparatus for controlling access by a set of accessing nodes to memory of a home node (in a multimode computer system) determines that each node in the set of nodes has accessed the memory, and forwards a completion message to each node in the set of nodes after it is determined that each node has accessed the memory. The completion message has data indicating that each node in the set of nodes has accessed the memory of the home node.

    摘要翻译： 用于控制一组访问节点对家庭节点（在多模式计算机系统中）的存储器的访问的方法和装置确定该组节点中的每个节点已经访问了存储器，并将完成消息转发到 在确定每个节点已访问存储器之后，节点集合。 完成消息具有指示节点集合中的每个节点已经访问了家庭节点的存储器的数据。

    Messaging facility with hardware tail pointer and software implemented head pointer message queue for distributed memory massively parallel processing system
    10.
    发明授权
    Messaging facility with hardware tail pointer and software implemented head pointer message queue for distributed memory massively parallel processing system 失效
    具有硬件尾部指针和软件的消息传递设施实现了分布式存储器大规模并行处理系统的头指针消息队列

    公开(公告)号：US5581705A

    公开(公告)日：1996-12-03

    申请号：US166443

    申请日：1993-12-13

    申请人： Randal S. Passint ,  Steven M. Oberlin ,  Eric C. Fromm

    发明人： Randal S. Passint ,  Steven M. Oberlin ,  Eric C. Fromm

    IPC分类号： G06F15/17 ,  G06F15/173 ,  G06F13/00 ,  G06F13/38 ,  G06F15/16

    CPC分类号： G06F15/17381

    摘要： A messaging facility is described that enables the passing of packets of data from one processing element to another in a globally addressable, distributed memory multiprocessor without having an explicit destination address in the target processing element's memory. The messaging facility can be used to accomplish a remote action by defining an opcode convention that permits one processor to send a message containing opcode, address and arguments to another. The destination processor, upon receiving the message after the arrival interrupt, can decode the opcode and perform the indicated action using the argument address and data. The messaging facility provides the primitives for the construction of an interprocessor communication protocol. Operating system communication and message-passing programming models can be accomplished using the messaging facility.

    摘要翻译： 描述了消息传送设施，其能够在全局可寻址的分布式存储器多处理器中将数据分组从一个处理元件传递到另一处理元件，而不在目标处理元件的存储器中具有明确的目的地地址。 通过定义一个允许一个处理器将包含操作码，地址和参数的消息发送到另一个处理器的操作码约定，消息传递设施可用于完成远程操作。 目的处理器在到达中断之后收到消息后，可以解码操作码，并使用参数地址和数据执行指示的动作。 消息传递设备提供了构建处理器间通信协议的原语。 操作系统通信和消息传递编程模型可以使用消息传递设备来实现。