公开(公告)号：US07361453B2

公开(公告)日：2008-04-22

申请号：US11081797

申请日：2005-03-15

申请人： Greja Johanna Adriana Maria Verheijden ,  Pascal Henri Leon Bancken ,  Johannes van Wingerden

发明人： Greja Johanna Adriana Maria Verheijden ,  Pascal Henri Leon Bancken ,  Johannes van Wingerden

IPC分类号： G03F7/00

CPC分类号： G03F7/0035 ,  G03F7/095 ,  H01L21/0332 ,  H01L21/0337 ,  H01L21/0338 ,  H01L21/31144

摘要： A method of manufacturing a semiconductor device with precision patterning is disclosed. A structure of a small dimension is created in a material, such as a semiconductor material, using a first and a second pattern, the patterns being identical but displaced over a distance with respect to each other. Two mask layers are used, wherein the first pattern is etched into the upper mask layer with a selective etch, and the second pattern is created on the upper mask layer or on the lower mask layer at locations where the upper mask layer has been removed. A part of the lower mask layer and/or the upper mask layer is etched according to the second pattern, resulting in a mask formed by remaining parts of the lower and upper mask layers, the mask having a structure with a dimension determined by a displacement of the second pattern with respect to the first pattern.

摘要翻译： 公开了一种制造精密图案化的半导体器件的方法。 使用第一和第二图案的材料（例如半导体材料）中产生小尺寸的结构，所述图案相同但相对于彼此间隔一定距离。 使用两个掩模层，其中通过选择性蚀刻将第一图案蚀刻到上掩模层中，并且在去除上掩模层的位置处，在上掩模层或下掩模层上形成第二图案。 根据第二图案蚀刻下掩模层和/或上掩模层的一部分，得到由下掩模层和上掩模层的剩余部分形成的掩模，掩模具有由位移确定的尺寸的结构 的第二图案相对于第一图案。

公开(公告)号：US06562694B2

公开(公告)日：2003-05-13

申请号：US09746027

申请日：2000-12-21

申请人： Ronald Dekker ,  Henricus Godefridus Rafael Maas ,  Cornelis Eustatius Timmering ,  Pascal Henri Leon Bancken

发明人： Ronald Dekker ,  Henricus Godefridus Rafael Maas ,  Cornelis Eustatius Timmering ,  Pascal Henri Leon Bancken

IPC分类号： H01L2176

CPC分类号： H01L21/76264 ,  H01L21/76283

摘要： A method of manufacturing a semiconductor device including semiconductor elements having semiconductor zones (17, 18, 24, 44, 45) formed in a top layer (4) of a silicon wafer (1) situated on a buried insulating layer (2). In this method, a first series of process steps are carried out, commonly referred to as front-end processing, wherein, inter alia, the silicon wafer is heated to temperatures above 700° C. Subsequently, trenches (25) are formed in the top layer, which extend as far as the buried insulating layer and do not intersect pn-junctions. After said trenches have been filled with insulating material (26, 29), the semiconductor device is completed in a second series of process steps, commonly referred to as back-end processing, wherein the temperature of the wafer does not exceed 400° C. The trenches are filled in a deposition process wherein the wafer is heated to a temperature which does not exceed 500° C. In this manner, a semiconductor device can be made comprising semiconductor elements having very small and shallow semiconductor zones.

摘要翻译： 一种制造半导体器件的方法，该半导体器件包括形成在位于掩埋绝缘层（2）上的硅晶片（1）的顶层（4）中的半导体区域（17,18,24,44,45）的半导体元件。 在该方法中，执行第一系列工艺步骤，通常称为前端处理，其中特别地，将硅晶片加热至高于700℃的温度。随后，形成沟槽（25） 顶层，其延伸至掩埋绝缘层并且不与pn结相交。 在所述沟槽已经填充有绝缘材料（26,29）之后，半导体器件在第二系列工艺步骤中完成，通常称为后端处理，其中晶片的温度不超过400℃。 在沉积工艺中填充沟槽，其中将晶片加热到不超过500℃的温度。以这种方式，可以制造半导体器件，其包括具有非常小且浅的半导体区域的半导体元件。