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156 条记录 (耗时 0.039 秒)

    Electrostatic Discharge (ESD) Protection Circuits
    4.
    发明申请
    Electrostatic Discharge (ESD) Protection Circuits 有权

    公开(公告)号：US20220337052A1

    公开(公告)日：2022-10-20

    申请号：US17721312

    申请日：2022-04-14

    申请人： Guobiao ZHANG ,  Zhitang SONG ,  Hongyu YU ,  Sannian SONG

    发明人： Guobiao ZHANG ,  Zhitang SONG ,  Hongyu YU ,  Sannian SONG

    IPC分类号： H02H9/00 ,  H02H9/02

    摘要： The present invention discloses parallel, series and hybrid ESD protection circuits. A preferred parallel ESD protection circuit comprises a plurality of ESD devices connected in parallel, with each comprising a resistor and an OTS component connected in series. A preferred series ESD protection circuit comprises a plurality of ESD devices connected in series, wherein the OTS components in all ESD devices are disposed on a same level. A preferred hybrid ESD protections circuit comprises ESD devices connected in parallel, as well as in series.

    Discrete Three-Dimensional Processor
    6.
    发明公开
    Discrete Three-Dimensional Processor 审中-公开

    公开(公告)号：US20230147647A1

    公开(公告)日：2023-05-11

    申请号：US18096013

    申请日：2023-01-12

    申请人： Guobiao ZHANG

    发明人： Guobiao ZHANG

    IPC分类号： G06N3/063 ,  G06F15/80

    CPC分类号： G06N3/063 ,  G06F15/803

    摘要： A discrete three-dimensional (3-D) processor a plurality of storage-processing units (SPU's), each of which comprises a non-memory circuit and more than one 3-D memory (3D-M) array. The preferred 3-D processor further comprises communicatively coupled first and second dice. The first die comprises the 3D-M arrays and the in-die peripheral-circuit components thereof; whereas, the second die comprises the non-memory circuits and off-die peripheral-circuit components of the 3D-M arrays.

    Hetero-Epitaxial Output Device Array
    7.
    发明申请
    Hetero-Epitaxial Output Device Array 审中-公开

    公开(公告)号：US20190198624A1

    公开(公告)日：2019-06-27

    申请号：US16231934

    申请日：2018-12-24

    申请人： Guobiao ZHANG ,  Peter Y. YU

    发明人： Guobiao ZHANG ,  Peter Y. YU

    IPC分类号： H01L29/20 ,  H01L27/088 ,  H01L23/00

    摘要： A GaN-on-Si output transistor array comprises a plurality of small monolithic output transistors. The substrate surface has multiple grids, upon which multiple pieces of the small monolithic GaN films are grown epitaxially on the silicon substrate. Each small monolithic output transistor is formed in a respective small monolithic GaN film. By disabling defective transistors, the overall yield/reliability is improved.

    Monolithic Three-Dimensional Pattern Processor
    9.
    发明申请
    Monolithic Three-Dimensional Pattern Processor 审中-公开

    公开(公告)号：US20190158510A1

    公开(公告)日：2019-05-23

    申请号：US16248914

    申请日：2019-01-16

    申请人： Guobiao ZHANG

    发明人： Guobiao ZHANG

    IPC分类号： H04L29/06 ,  G10L15/34 ,  G06F21/56 ,  G06F16/903

    摘要： A monolithic three-dimensional (3-D) pattern processor comprises a plurality of storage-processing units (SPU's). Each of the SPU's comprises at least a 3-D memory (3D-M) array and a pattern-processing circuit. The 3D-M could be a horizontal 3D-M (3D-MH) or a vertical 3D-M (3D-MV). The 3D-M array stores patterns; the pattern-processing circuit processes these patterns; and, they are communicatively coupled by a plurality of intra-die connections.

    Configurable Computing Array
    10.
    发明申请
    Configurable Computing Array 审中-公开

    公开(公告)号：US20190158095A1

    公开(公告)日：2019-05-23

    申请号：US16186571

    申请日：2018-11-11

    申请人： Guobiao ZHANG

    发明人： Guobiao ZHANG

    IPC分类号： H03K19/177 ,  H03K19/173 ,  G11C5/02

    摘要： A configurable computing array comprises at least an array of configurable interconnects, at least an array of configurable logic elements and at least an array of configurable computing elements. Each configurable computing element comprises at least a programmable memory for storing a look-up table (LUT) for a math function.