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公开(公告)号：US06240474B1
公开(公告)日：2001-05-29
申请号：US08931705
申请日：1997-09-16
IPC分类号： G06F1314
CPC分类号： G06F13/28 , G06F13/4027
摘要： A methodology and implementing system are provided in which pipelined read transfers or PRTs are implemented. The PRTs include a request phase and a response phase. The PRT request phase involves a PRT request master delivering to a PRT request target, a source address, a destination address and the transfer size for the data being requested. In the PRT response phase, the PRT request target becomes a PRT response master, i.e. a PCI bus master, and initiates a completion of the transaction that was requested in the originating PRT request.
摘要翻译： 提供了一种实现流水线读取传输或PRT的方法和实现系统。 PRT包括请求阶段和响应阶段。 PRT请求阶段涉及PRT请求主机传送到PRT请求目标，源地址，目的地地址和正在请求的数据的传输大小。 在PRT响应阶段，PRT请求目标成为PRT响应主机，即PCI总线主机，并启动完成在发起PRT请求中请求的事务。
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公开(公告)号：US06175888B1
公开(公告)日：2001-01-16
申请号：US08627810
申请日：1996-04-10
IPC分类号： G06F1314
CPC分类号： G06F13/36 , G06F13/4027
摘要： A data processing system includes a processor, system memory and a number of peripheral devices, and one or more bridges which may connect between the processor, memory and peripheral devices and other hosts or peripheral devices such as in a network. A bridge, such as a PCI host bridge, connects between a primary bus (e.g system bus) and a secondary bus. The host bridge provides a dual host bridge function which creates two secondary bus interfaces. This allows increased loading capability under one dual host bridge compared to a lesser number of slots allowed under one normal host bridge. Also included is additional control logic for providing arbitration control and for steering transactions to the appropriate bus interface. Additionally, peer to peer support across the two secondary bus interfaces in provided.
摘要翻译： 数据处理系统包括处理器，系统存储器和多个外围设备以及可以在处理器，存储器和外围设备以及诸如网络中的其它主机或外围设备之间连接的一个或多个桥接器。 诸如PCI主机桥的桥连接在主总线（例如系统总线）和辅助总线之间。 主桥提供双主机桥功能，其创建两个辅助总线接口。 这允许在一个双主机桥下增加负载能力，而在一个正常主桥下允许的较少数量的时隙。 还包括附加的控制逻辑，用于提供仲裁控制和用于转向事务到适当的总线接口。 另外，提供的两个辅助总线接口的对等支持。
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3.发明授权Method and system for interrupt handling using device pipelined packet transfers 失效使用设备流水线分组传输的中断处理方法和系统公开(公告)号：US06493779B1
公开(公告)日：2002-12-10
申请号：US09224111
申请日：1998-12-21
IPC分类号： G06F1324
CPC分类号： G06F13/24
摘要： A method and apparatus is provided in which Pipelined Packet Transfers (PPT) are implemented. The PPT methodology includes a request phase and a response phase. The PPT request phase involves a PPT request master delivering to a PPT request target a source address, a destination address and an information packet for the interrupt being requested. The PPT response phase involves the PPT request target becoming a PPT response master with the PPT response master delivering to a PPT request master a destination address and a data packet which includes the interrupt processing information. Pipelined Packet transfers (PPT) are ordered in accordance with a predetermined processing priority to improve performance and avoid deadlock.
摘要翻译： 提供了一种实现流水线分组传输（PPT）的方法和装置。 PPT方法包括请求阶段和响应阶段。 PPT请求阶段涉及PPT请求主机，向PPT请求目标传送要求的中断的源地址，目的地地址和信息分组。 PPT响应阶段涉及PPT请求目标成为PPT响应主机，PPT响应主机向PPT请求主机传递目的地地址和包括中断处理信息的数据分组。 流水线分组传输（PPT）根据预定的处理优先级进行排序，以提高性能并避免死锁。
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4.发明授权Method and system for interrupt handling using system pipelined packet transfers 失效使用系统流水线分组传输的中断处理方法和系统公开(公告)号：US06418497B1
公开(公告)日：2002-07-09
申请号：US09224119
申请日：1998-12-21
IPC分类号： G06F948
CPC分类号： G06F13/26
摘要： A method and apparatus is provided in which Pipelined Packet Transfers (PPT) are implemented. The PPT methodology includes a request phase and a response phase. The PPT request phase involves a PPT request master delivering to a PPT request target a source address, a destination address and an information packet for the interrupt being requested. The PPT response phase involves the PPT request target becoming a PPT response master with the PPT response master delivering to a PPT request master a destination address and a data packet which includes the interrupt processing information. Pipelined Packet transfers (PPT) are ordered in accordance with a predetermined processing priority to improve performance and avoid deadlock.
摘要翻译： 提供了一种实现流水线分组传输（PPT）的方法和装置。 PPT方法包括请求阶段和响应阶段。 PPT请求阶段涉及PPT请求主机，向PPT请求目标传送要求的中断的源地址，目的地地址和信息分组。 PPT响应阶段涉及PPT请求目标成为PPT响应主机，PPT响应主机向PPT请求主机传递目的地地址和包括中断处理信息的数据分组。 流水线分组传输（PPT）根据预定的处理优先级进行排序，以提高性能并避免死锁。
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公开(公告)号：US06327636B1
公开(公告)日：2001-12-04
申请号：US08931706
申请日：1997-09-16
IPC分类号： G06F13368
CPC分类号： G06F13/368
摘要： A methodology and implementing system are provided in which pipelined read transfers or PRTs are implemented. The PRTs include a request phase and a response phase. The PRT request phase involves a PRT request master delivering to a PRT request target, a source address, a destination address and the transfer size for the data being requested. In the PRT response phase, the PRT request target becomes a PRT response master, i.e. a PCI bus master, and initiates a completion of the transaction that was requested in the originating PRT request. Pipelined read transfers are ordered in accordance with a predetermined processing priority to improve performance and avoid deadlocks.
摘要翻译： 提供了一种实现流水线读取传输或PRT的方法和实现系统。 PRT包括请求阶段和响应阶段。 PRT请求阶段涉及PRT请求主机传送到PRT请求目标，源地址，目的地地址和正在请求的数据的传输大小。 在PRT响应阶段，PRT请求目标成为PRT响应主机，即PCI总线主机，并启动完成在发起PRT请求中请求的事务。 流水线读取传输根据预定的处理优先级进行排序以提高性能并避免死锁。
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公开(公告)号：US5978869A
公开(公告)日：1999-11-02
申请号：US897573
申请日：1997-07-21
CPC分类号： G06F13/4217 , G06F1/08
摘要： A methodology and implementing system 101 are provided in which a PCI bus is enhanced to operate at a plurality of data transfer speeds, including for example, 133 MHz in order to accommodate subsystem boards operating at higher frequencies, while at the same time allowing normal 66 MHz PCI clocking for devices designed to operate at the lower 66 MHz standard PCI speed. Master strobe MSTB 303, 403 and target strobe TSTB signals 309, 411 are generated in a handshaking methodology to determine if a master data transaction requesting device and a target data transaction device are designed to operate at the higher data transfer frequency. Higher frequency capable devices or boards are run at the increased frequency when both the requesting master and the selected target devices request the higher transfer rate, and standard devices or boards are run at the lower standard PCI frequency, while both master and target devices are coupled to and run from the same multi-speed PCI bus 125.
摘要翻译： 提供了一种方法和实现系统101，其中PCI总线被增强以以多个数据传输速度操作，包括例如133MHz，以便容纳在较高频率下工作的子系统板，同时允许正常的66 设计用于在66 MHz标准PCI速度下运行的设备的MHz PCI时钟。 在握手方法中产生主选通MSTB 303,403和目标选通TSTB信号309,411，以确定主数据交易请求装置和目标数据交易装置是否被设计为在较高数据传输频率下操作。 当请求主机和所选择的目标设备请求更高的传输速率时，较高频率的设备或板以增加的频率运行，并且标准设备或板以较低的标准PCI频率运行，而主设备和目标设备都耦合 从同一个多速PCI总线125运行并运行。
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7.发明授权Method and system for translating peripheral component interconnect (PCI) peer-to-peer access across multiple PCI host bridges within a computer system 失效用于在计算机系统内跨多个PCI主机桥转换外围组件互连（PCI）对等访问的方法和系统
公开(公告)号：US5898888A
公开(公告)日：1999-04-27
申请号：US766737
申请日：1996-12-13
IPC分类号： G06F13/40
CPC分类号： G06F13/4036
摘要： A method and system for translating peer-to-peer access across multiple Peripheral Component Interconnect (PCI) host bridges within a data-processing system are disclosed. In accordance with the method and system of the present invention, a processor and a system memory are connected to a system bus. A first and at least a second PCI local buses are also connected to the system bus via a first PCI host bridge and a second PCI host bridge, respectively. The two PCI local buses have bus transaction protocols that are different from those of the system bus. At least one PCI device is connected to each of the two PCI local buses, and shares data with the processor and the system memory. In addition, each PCI device shares data with the other PCI device as peer-to-peer devices across multiple PCI host bridges. A sequence of transactions is controlled through the two PCI host bridges to prevent a deadlock condition by not allowing a subsequent peer-to-peer write request destined for one of the two PCI local buses to be blocked from making progress through the two PCI host bridges.
摘要翻译： 公开了一种用于在数据处理系统内跨多个外围组件互连（PCI）主机桥转换对等接入的方法和系统。 根据本发明的方法和系统，处理器和系统存储器连接到系统总线。 第一和至少第二PCI本地总线也分别经由第一PCI主机桥和第二PCI主机桥连接到系统总线。 两个PCI本地总线具有与系统总线不同的总线事务协议。 至少一个PCI设备连接到两个PCI本地总线中的每一个，并与处理器和系统存储器共享数据。 此外，每个PCI设备与另一个PCI设备共享数据，作为跨多个PCI主机桥的对等设备。 一系列事务通过两个PCI主机桥进行控制，以防止死锁状况不允许发往目的地为两个PCI本地总线之一的后续对等写入请求阻止通过两个PCI主机桥进行 。
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8.发明授权System and method for enhancement of system bus to mezzanine bus transactions 失效将系统总线增强到夹层总线交易的系统和方法
公开(公告)号：US5673399A
公开(公告)日：1997-09-30
申请号：US552034
申请日：1995-11-02
CPC分类号： G06F13/4027
摘要： A data processing system includes a host processor, a number of peripheral devices, and one or more bridges which may connect between the host, peripheral devices and other hosts or peripheral devices such as in a network. Each bridge, such as a PCI host bridge, connects between a primary bus (e.g system bus) and a secondary bus wherein for the purpose of clarity, the primary bus will be considered as the source for outbound transactions and the destination for inbound transactions and the secondary bus would be considered the destination for outbound transactions and the source for inbound transactions. The host bridge includes an outbound data path, an inbound data path, and a control mechanism. The outbound data path includes a queued buffer for storing transactions in order of receipt from the primary bus where the requests in the queued buffer may be mixed as between read requests and write transactions, the outbound path also includes a number of parallel buffers for storing read reply data and address information. The inbound path is a mirror image of the outbound path with read requests and write requests being stored in a sequential buffer and read replies being stored in a number of parallel buffers. Both the inbound path and the outbound path in the host bridge are controlled by a state machine which takes into consideration activity in both directions and permits or inhibits bypass transactions based on the protocol of the buses being interconnected through the bridge.
摘要翻译： 数据处理系统包括主处理器，多个外围设备以及可以在主机，外围设备和其他主机或诸如网络中的外围设备之间连接的一个或多个网桥。 每个桥梁（如PCI主机桥）连接在主总线（例如系统总线）和辅助总线之间，为了清楚起见，主总线将被视为出站事务的来源和入站事务的目的地， 辅助总线将被视为出站交易的目的地和入站交易的来源。 主桥包括出站数据路径，入站数据路径和控制机制。 出站数据路径包括排队缓冲器，用于按照从主总线接收的顺序存储事务，其中排队缓冲器中的请求可以在读请求和写事务之间混合，出站路径还包括多个用于存储读取的并行缓冲器 回复数据和地址信息。 入站路径是出站路径的镜像，读取请求和写入请求存储在顺序缓冲区中，并且读取回复存储在多个并行缓冲区中。 主桥中的入站路径和出站路径都由状态机控制，该状态机考虑到两个方向的活动，并且基于通过桥互连的总线的协议允许或禁止旁路交易。
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9.发明授权Method and system for increasing the load and expansion capabilities of a bus through the use of in-line switches 失效通过使用在线开关增加总线的负载和扩展能力的方法和系统
公开(公告)号：US5887144A
公开(公告)日：1999-03-23
申请号：US753116
申请日：1996-11-20
CPC分类号： G06F13/4068
摘要： A method and system for expanding the load capabilities of a bus, such as the PCI bus. The system includes a primary bus, a plurality of secondary buses for connecting additional devices, a plurality of in-line switches, an arbiter, and control logic means. The plurality of in-line switches are used for connecting the primary bus to a corresponding one of the secondary buses, each one of the switches having an enable line for receiving a signal to enable or disable the switch. The arbiter is used for receiving requests for control of the primary bus, and for selecting one of the requests as a master for the control. The control logic means is used for enabling and disabling each of the switches, via the corresponding enable line, for connection or disconnection to the primary bus. The control logic means includes means, coupled to the arbiter, for gaining control over the primary bus prior to granting control to the master, and means for transmitting, during control over the primary bus, an enable signal to the switches corresponding to the secondary buses desired to be connected to the primary bus.
摘要翻译： 一种用于扩展总线（如PCI总线）的负载能力的方法和系统。 该系统包括主总线，用于连接附加设备的多个次总线，多个在线交换机，仲裁器和控制逻辑装置。 多个在线开关用于将主总线连接到相应的一个辅助总线，每个开关具有用于接收信号以启用或禁用开关的使能线。 仲裁器用于接收对主总线的控制请求，并用于选择其中一个请求作为控制主机。 控制逻辑装置用于通过相应的使能线路使能和禁用每个开关用于连接或断开到主总线。 控制逻辑装置包括耦合到仲裁器的装置，用于在向主机授予控制之前获得对主总线的控制，以及用于在对主总线进行控制期间向对应于辅助总线的开关发送使能信号的装置 希望连接到主总线。
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10.发明授权Method and apparatus for adding and removing components of a data processing system without powering down 失效用于在不掉电的情况下添加和移除数据处理系统的组件的方法和装置
公开(公告)号：US5784576A
公开(公告)日：1998-07-21
申请号：US741466
申请日：1996-10-31
IPC分类号： G06F13/40 , G06F13/00 , H03K17/693 , H04B1/44
CPC分类号： G06F13/4081
摘要： A method and system for providing the ability to add or remove components of a data processing system without powering the system down ("Hot-plug"). The system includes an arbiter, residing within a Host Bridge, Control & Power logic, and a plurality of in-line switch modules coupled to a bus. Each of the in-line switch modules provide isolation for load(s) connected thereto. The Host Bridge in combination with the Control & Power Logic implement the Hot-plug operations such as ramping up and down of the power to a selected slot, and activating the appropriate in-line switches for communication from/to a load (target/controlling master).
摘要翻译： 一种方法和系统，用于提供在不向系统供电的情况下添加或删除数据处理系统的组件的能力（“热插拔”）。 该系统包括驻留在主机桥中的仲裁器，控制和电源逻辑以及耦合到总线的多个在线开关模块。 每个在线开关模块为连接到其上的负载提供隔离。 主机桥与控制和电源逻辑结合实施热插拔操作，例如将功率上升和下降到选定的插槽，并激活适当的在线开关以进行从负载（目标/控制）的通信 主）。
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