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    Method for optimally converting a circuit design into a semiconductor device
    1.
    发明申请
    Method for optimally converting a circuit design into a semiconductor device 有权
    将电路设计最佳地转换为半导体器件的方法

    公开(公告)号：US20070006117A1

    公开(公告)日：2007-01-04

    申请号：US11333925

    申请日：2006-01-18

    申请人： Gwan Chang ,  Ru-Gun Liu ,  Chih-Ming Lai ,  Yung-Chin Hou

    发明人： Gwan Chang ,  Ru-Gun Liu ,  Chih-Ming Lai ,  Yung-Chin Hou

    IPC分类号： G06F17/50

    CPC分类号： G06F17/5068

    摘要： A method for converting a circuit design into a semiconductor device includes the following steps. A first set of deign information is provided for representing the circuit design. Priority design information, which represents a priority portion of the circuit design, is extracted from the first set of design information. The priority design information is processed for generating a second set of design information. The semiconductor device is fabricated based on the first and second sets of design information. The second set of design information contains enhanced fabrication conditions as opposed to those of the first set of design information for optimizing the conversion of the circuit design into the semiconductor device.

    摘要翻译： 将电路设计转换为半导体器件的方法包括以下步骤。 提供第一组设计信息以表示电路设计。 从第一组设计信息中提取代表电路设计的优先级部分的优先级设计信息。 优先设计信息被处理以产生第二组设计信息。 基于第一和第二组设计信息制造半导体器件。 与用于优化电路设计到半导体器件的转换的第一组设计信息相比，第二组设计信息包含增强的制造条件。

    Method for optimally converting a circuit design into a semiconductor device
    3.
    发明授权
    Method for optimally converting a circuit design into a semiconductor device 有权
    将电路设计最佳地转换为半导体器件的方法

    公开(公告)号：US07797668B2

    公开(公告)日：2010-09-14

    申请号：US11333925

    申请日：2006-01-18

    申请人： Gwan Sin Chang ,  Ru-Gun Liu ,  Chih-Ming Lai ,  Yung-Chin Hou

    发明人： Gwan Sin Chang ,  Ru-Gun Liu ,  Chih-Ming Lai ,  Yung-Chin Hou

    IPC分类号： G06F17/50 ,  G06F9/45

    CPC分类号： G06F17/5068

    摘要： A method for converting a circuit design into a semiconductor device includes the following steps. A first set of deign information is provided for representing the circuit design. Priority design information, which represents a priority portion of the circuit design, is extracted from the first set of design information. The priority design information is processed for generating a second set of design information. The semiconductor device is fabricated based on the first and second sets of design information. The second set of design information contains enhanced fabrication conditions as opposed to those of the first set of design information for optimizing the conversion of the circuit design into the semiconductor device.

    摘要翻译： 将电路设计转换为半导体器件的方法包括以下步骤。 提供第一组设计信息以表示电路设计。 从第一组设计信息中提取代表电路设计的优先级部分的优先级设计信息。 优先设计信息被处理以产生第二组设计信息。 基于第一和第二组设计信息制造半导体器件。 与用于优化电路设计到半导体器件的转换的第一组设计信息相比，第二组设计信息包含增强的制造条件。

    SEMICONDUCTOR INTERCONNECT STRUCTURE
    6.
    发明申请
    SEMICONDUCTOR INTERCONNECT STRUCTURE 审中-公开

    公开(公告)号：US20130292841A1

    公开(公告)日：2013-11-07

    申请号：US13464055

    申请日：2012-05-04

    申请人： Chih-Ming Lai ,  Wen-Chun Huang ,  Ru-Gun Liu ,  Pi-Tsung Chen

    发明人： Chih-Ming Lai ,  Wen-Chun Huang ,  Ru-Gun Liu ,  Pi-Tsung Chen

    IPC分类号： H01L21/768 ,  H01L23/48

    CPC分类号： H01L23/5226 ,  H01L21/76816 ,  H01L23/5283 ,  H01L23/5329 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

    摘要： The present disclosure provides an interconnect structure for a semiconductor device. The interconnect structure includes a first metal layer that contains a first metal line. The interconnect structure includes a dielectric layer located over the first metal layer. The dielectric layer contains a first sub-via electrically coupled to the first metal line and a second sub-via electrically coupled to the first sub-via. The second sub-via is different from the first sub-via. The interconnect structure includes a second metal layer located over the dielectric layer. The second metal layer contains a second metal line electrically coupled to the second sub-via. No other metal layer is located between the first metal layer and the second metal layer.

    摘要翻译： 本公开提供了一种用于半导体器件的互连结构。 互连结构包括含有第一金属线的第一金属层。 互连结构包括位于第一金属层上方的电介质层。 电介质层包含电耦合到第一金属线的第一子通路和电耦合到第一子通路的第二子通路。 第二子通孔不同于第一子通孔。 互连结构包括位于电介质层上方的第二金属层。 第二金属层包含电耦合到第二子通孔的第二金属线。 第一金属层和第二金属层之间没有其他金属层。

    Method, Apparatus, and System for LPC Hot Spot Fix
    9.
    发明申请
    Method, Apparatus, and System for LPC Hot Spot Fix 有权
    LPC热点固定的方法，装置和系统

    公开(公告)号：US20070266352A1

    公开(公告)日：2007-11-15

    申请号：US11689197

    申请日：2007-03-21

    申请人： Yi-Kan Cheng ,  Chih-Ming Lai ,  Ru-Gun Liu

    发明人： Yi-Kan Cheng ,  Chih-Ming Lai ,  Ru-Gun Liu

    IPC分类号： G06F17/50

    CPC分类号： G06F17/5077

    摘要： Efficient and cost-effective systems and methods for detecting and correcting hot spots of semiconductor devices are disclosed. In one aspect, a method for creating a layout from a circuit design is described. The method includes applying a first set of hot spot conditions to a global route to produce a detailed route; applying a second set of hot spot conditions to the detailed route to produce a post-detailed route; and applying a third set of hot spot conditions to the post-detailed route to produce the layout. In another aspect, a method includes providing a circuit design; applying a first hot spot filter to a global routing of the circuit design to produce a detailed route; applying a less pessimistic, second hot spot filter to the detailed route to produce a post-detailed route; and performing a rip-up and reroute of the post-detailed route to produce a final layout.

    摘要翻译： 公开了用于检测和校正半导体器件的热点的高效且成本有效的系统和方法。 在一个方面，描述了一种用于从电路设计创建布局的方法。 该方法包括将第一组热点条件应用于全局路由以产生详细路由; 将第二组热点条件应用于详细路线以产生后详细路线; 以及将第三组热点条件应用于后详细路线以产生布局。 另一方面，一种方法包括提供电路设计; 将第一热点滤波器应用于电路设计的全局路由以产生详细的路由; 在详细的路线上应用较不悲观的第二热点过滤器，以产生详细的路线; 并执行后期详细路线的撤销和重新路线以产生最终布局。

    MODEL IMPORT FOR ELECTRONIC DESIGN AUTOMATION
    10.
    发明申请
    MODEL IMPORT FOR ELECTRONIC DESIGN AUTOMATION 有权
    电子设计自动化模型进口

    公开(公告)号：US20110231804A1

    公开(公告)日：2011-09-22

    申请号：US13116981

    申请日：2011-05-26

    申请人： Ru-Gun Liu ,  Chih-Ming Lai ,  Wen-Chun Huang ,  Boren Luo ,  I-Chang Shin ,  Yao-Ching Ku ,  Cliff Hou

    发明人： Ru-Gun Liu ,  Chih-Ming Lai ,  Wen-Chun Huang ,  Boren Luo ,  I-Chang Shin ,  Yao-Ching Ku ,  Cliff Hou

    IPC分类号： G06F17/50

    CPC分类号： G06F17/50

    摘要： Methods and systems for providing processing parameters in a secure format are disclosed. In one aspect, a method for providing semiconductor fabrication processing parameters to a design facility is disclosed. The method comprises providing a set of processing parameters of a fabrication facility; creating a model from the set of processing parameters; converting the model into a corresponding set of kernels; converting the set of kernels into a corresponding set of matrices; and communicating the set of matrices to the design facility. In another aspect, a method for providing semiconductor fabrication processing parameters is disclosed. The method comprises providing a set of processing parameters of a fabrication facility; creating a processing model from the set of processing parameters; encrypting the processing model into a format for use with a plurality of EDA tools; and communicating the encrypted processing model format to a design facility.

    摘要翻译： 公开了以安全格式提供处理参数的方法和系统。 一方面，公开了一种向设计设备提供半导体制造处理参数的方法。 该方法包括提供制造设施的一组处理参数; 从一组处理参数创建模型; 将模型转换为相应的一组内核; 将所述内核集合转换成相应的矩阵集合; 并将该组矩阵传送到设计设施。 另一方面，公开了一种用于提供半导体制造处理参数的方法。 该方法包括提供制造设施的一组处理参数; 从一组处理参数创建一个处理模型; 将处理模型加密成与多个EDA工具一起使用的格式; 并将加密的处理模型格式传送到设计设施。