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公开(公告)号：US20090187866A1
公开(公告)日：2009-07-23
申请号：US12016661
申请日：2008-01-18
申请人： Tsong-Hua Ou , Ying-Chou Cheng , Chia-Chi Lin , Ru-Gun Liu , Chih-Ming Lai , Min-Hong Wu , Yih-Yuh Doong , Cliff Hou , Yao-Ching Ku
发明人： Tsong-Hua Ou , Ying-Chou Cheng , Chia-Chi Lin , Ru-Gun Liu , Chih-Ming Lai , Min-Hong Wu , Yih-Yuh Doong , Cliff Hou , Yao-Ching Ku
IPC分类号： G06F17/50
CPC分类号： G06F17/5009 , G06F17/5036 , G06F2217/80
摘要： A system, method, and computer readable medium for generating a parameterized and characterized pattern library for use in extracting parasitics from an integrated circuit design is provided. In an embodiment, a layout of an interconnect pattern is provided. A process simulation may be performed on the interconnect pattern. In a further embodiment, the interconnect pattern is dissected into a plurality of segments taking into account OPC rules. A parasitic resistance and/or parasitic capacitance associated with the interconnect pattern may be determined by a physical model and/or field solver.
摘要翻译： 提供了一种用于从集成电路设计中产生用于提取寄生效应的参数化和表征的模式库的系统，方法和计算机可读介质。 在一个实施例中，提供了互连图案的布局。 可以在互连图案上执行过程模拟。 在另一实施例中，考虑到OPC规则，将互连图案解剖成多个段。 与互连图案相关联的寄生电阻和/或寄生电容可由物理模型和/或场求解器确定。
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公开(公告)号：US07783999B2
公开(公告)日：2010-08-24
申请号：US12016661
申请日：2008-01-18
申请人： Tsong-Hua Ou , Ying-Chou Cheng , Chia-Chi Lin , Ru-Gun Liu , Chih-Ming Lai , Min-Hong Wu , Yih-Yuh Doong , Cliff Hou , Yao-Ching Ku
发明人： Tsong-Hua Ou , Ying-Chou Cheng , Chia-Chi Lin , Ru-Gun Liu , Chih-Ming Lai , Min-Hong Wu , Yih-Yuh Doong , Cliff Hou , Yao-Ching Ku
IPC分类号： G06F17/50
CPC分类号： G06F17/5009 , G06F17/5036 , G06F2217/80
摘要： A system, method, and computer readable medium for generating a parameterized and characterized pattern library for use in extracting parasitics from an integrated circuit design is provided. In an embodiment, a layout of an interconnect pattern is provided. A process simulation may be performed on the interconnect pattern. In a further embodiment, the interconnect pattern is dissected into a plurality of segments taking into account OPC rules. A parasitic resistance and/or parasitic capacitance associated with the interconnect pattern may be determined by a physical model and/or field solver.
摘要翻译： 提供了一种用于从集成电路设计中产生用于提取寄生效应的参数化和表征的模式库的系统，方法和计算机可读介质。 在一个实施例中，提供了互连图案的布局。 可以在互连图案上执行过程模拟。 在另一实施例中，考虑到OPC规则，将互连图案解剖成多个段。 与互连图案相关联的寄生电阻和/或寄生电容可由物理模型和/或场求解器确定。
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公开(公告)号：US08037575B2
公开(公告)日：2011-10-18
申请号：US12211624
申请日：2008-09-16
申请人： Ying-Chou Cheng , Chih-Ming Lai , Ru-Gun Liu , Tsong-Hua Ou , Min-Hong Wu , Yih-Yuh Doong , Hsiao-Shu Chao , Yi-Kan Cheng , Yao-Ching Ku , Cliff Hou
发明人： Ying-Chou Cheng , Chih-Ming Lai , Ru-Gun Liu , Tsong-Hua Ou , Min-Hong Wu , Yih-Yuh Doong , Hsiao-Shu Chao , Yi-Kan Cheng , Yao-Ching Ku , Cliff Hou
IPC分类号： G06F17/50
CPC分类号： G06F17/5036 , G06F2217/12 , Y02P90/265 , Y10T16/2771
摘要： An integrated circuit (IC) design method includes providing an IC layout contour based on an IC design layout of an IC device and IC manufacturing data; generating an effective rectangle layout to represent the IC layout contour; and simulating the IC device using the effective rectangular layout.
摘要翻译： 集成电路（IC）设计方法包括基于IC器件的IC设计布局和IC制造数据提供IC布局轮廓; 生成有效的矩形布局来表示IC布局轮廓; 并使用有效的矩形布局模拟IC器件。
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公开(公告)号：US08001494B2
公开(公告)日：2011-08-16
申请号：US12250424
申请日：2008-10-13
申请人： Yung-Chin Hou , Ying-Chou Cheng , Ru-Gun Liu , Chih-Ming Lai , Yi-Kan Cheng , Chung-Kai Lin , Hsiao-Shu Chao , Ping-Heng Yeh , Min-Hong Wu , Yao-Ching Ku , Tsong-Hua Ou
发明人： Yung-Chin Hou , Ying-Chou Cheng , Ru-Gun Liu , Chih-Ming Lai , Yi-Kan Cheng , Chung-Kai Lin , Hsiao-Shu Chao , Ping-Heng Yeh , Min-Hong Wu , Yao-Ching Ku , Tsong-Hua Ou
IPC分类号： G06F17/50
CPC分类号： G06F17/5036 , G06F17/5081
摘要： Disclosed is a system and method for integrated circuit designs and post layout analysis. The integrated circuit design method includes providing a plurality of IC devices with various design dimensions; collecting electrical performance data of the IC devices; extracting equivalent dimensions of the IC devices; generating a shape related model to relate the equivalent dimensions to the electrical performance data of the IC devices; and creating a data refinement table using the equivalent dimensions and the electrical performance data.
摘要翻译： 公开了一种用于集成电路设计和后期布局分析的系统和方法。 集成电路设计方法包括提供具有各种设计尺寸的多个IC器件; 收集IC器件的电气性能数据; 提取IC器件的等效尺寸; 产生形状相关模型以将等效尺寸与IC器件的电性能数据相关联; 以及使用等效尺寸和电气性能数据创建数据细化表。
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公开(公告)号：US08201111B2
公开(公告)日：2012-06-12
申请号：US13195907
申请日：2011-08-02
申请人： Yung-Chin Hou , Ying-Chou Cheng , Ru-Gun Liu , Chih-Ming Lai , Yi-Kan Cheng , Chung-Kai Lin , Hsiao-Shu Chao , Ping-Heng Yeh , Min-Hong Wu , Yao-Ching Ku , Tsong-Hua Ou
发明人： Yung-Chin Hou , Ying-Chou Cheng , Ru-Gun Liu , Chih-Ming Lai , Yi-Kan Cheng , Chung-Kai Lin , Hsiao-Shu Chao , Ping-Heng Yeh , Min-Hong Wu , Yao-Ching Ku , Tsong-Hua Ou
IPC分类号： G06F17/50
CPC分类号： G06F17/5036 , G06F17/5081
摘要： Disclosed is a system and method for integrated circuit designs and post layout analysis. The integrated circuit design method includes providing a plurality of IC devices with various design dimensions; collecting electrical performance data of the IC devices; extracting equivalent dimensions of the IC devices; generating a shape related model to relate the equivalent dimensions to the electrical performance data of the IC devices; and creating a data refinement table using the equivalent dimensions and the electrical performance data.
摘要翻译： 公开了一种用于集成电路设计和后期布局分析的系统和方法。 集成电路设计方法包括提供具有各种设计尺寸的多个IC器件; 收集IC器件的电气性能数据; 提取IC器件的等效尺寸; 产生形状相关模型以将等效尺寸与IC器件的电性能数据相关联; 以及使用等效尺寸和电气性能数据创建数据细化表。
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公开(公告)号：US20110289466A1
公开(公告)日：2011-11-24
申请号：US13195907
申请日：2011-08-02
申请人： Yung-Chin Hou , Ying-Chou Cheng , Ru-Gun Liu , Chih-Ming Lai , Yi-Kan Cheng , Chung-Kai Lin , Hsiao-Shu Chao , Ping-Heng Yeh , Min-Hong Wu , Yao-Ching Ku , Tsong-Hua Ou
发明人： Yung-Chin Hou , Ying-Chou Cheng , Ru-Gun Liu , Chih-Ming Lai , Yi-Kan Cheng , Chung-Kai Lin , Hsiao-Shu Chao , Ping-Heng Yeh , Min-Hong Wu , Yao-Ching Ku , Tsong-Hua Ou
IPC分类号： G06F17/50
CPC分类号： G06F17/5036 , G06F17/5081
摘要： Disclosed is a system and method for integrated circuit designs and post layout analysis. The integrated circuit design method includes providing a plurality of IC devices with various design dimensions; collecting electrical performance data of the IC devices; extracting equivalent dimensions of the IC devices; generating a shape related model to relate the equivalent dimensions to the electrical performance data of the IC devices; and creating a data refinement table using the equivalent dimensions and the electrical performance data.
摘要翻译： 公开了一种用于集成电路设计和后期布局分析的系统和方法。 集成电路设计方法包括提供具有各种设计尺寸的多个IC器件; 收集IC器件的电气性能数据; 提取IC器件的等效尺寸; 产生形状相关模型以将等效尺寸与IC器件的电性能数据相关联; 以及使用等效尺寸和电气性能数据创建数据细化表。
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公开(公告)号：US08673520B2
公开(公告)日：2014-03-18
申请号：US13046265
申请日：2011-03-11
申请人： George Liu , Kuei Shun Chen , Chih-Yang Yeh , Te-Chih Huang , Wen-Hao Liu , Ying-Chou Cheng , Boren Luo , Tsong-Hua Ou , Yu-Po Tang , Wen-Chun Huang , Ru-Gun Liu , Shu-Chen Lu , Yu Lun Liu , Yao-Ching Ku , Tsai-Sheng Gau
发明人： George Liu , Kuei Shun Chen , Chih-Yang Yeh , Te-Chih Huang , Wen-Hao Liu , Ying-Chou Cheng , Boren Luo , Tsong-Hua Ou , Yu-Po Tang , Wen-Chun Huang , Ru-Gun Liu , Shu-Chen Lu , Yu Lun Liu , Yao-Ching Ku , Tsai-Sheng Gau
IPC分类号： G03F1/00
CPC分类号： G06F17/5068 , G03F1/00 , G03F1/68
摘要： An intensity selective exposure photomask, also describes as a gradated photomask, is provided. The photomask includes a first region including a first array of sub-resolution features. The first region blocks a first percentage of the incident radiation. The photomask also includes a second region including a second array of sub-resolution features. The second region blocks a second percentage of the incident radiation different that the first percentage. Each of the features of the first and second array includes an opening disposed in an area of attenuating material.
摘要翻译： 还提供强度选择性曝光光掩模，还描述为渐变光掩模。 光掩模包括包括第一子分解特征阵列的第一区域。 第一个区域阻止了第一个入射辐射的百分比。 光掩模还包括包括第二子分辨率特征阵列的第二区域。 第二个区域阻止了第二个百分比的入射辐射不同于第一个百分比。 第一和第二阵列的每个特征包括设置在衰减材料区域中的开口。
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公开(公告)号：US20120040278A1
公开(公告)日：2012-02-16
申请号：US13281198
申请日：2011-10-25
申请人： George Liu , Kuei Shun Chen , Chih-Yang Yeh , Te-Chih Huang , Wen-Hao Liu , Ying-Chou Cheng , Boren Luo , Tsong-Hua Ou , Yu-Po Tang , Wen-Chun Huang , Ru-Gun Liu , Shu-Chen Lu , Yu Lun Liu , Yao-Ching Ku , Tsai-Sheng Gau
发明人： George Liu , Kuei Shun Chen , Chih-Yang Yeh , Te-Chih Huang , Wen-Hao Liu , Ying-Chou Cheng , Boren Luo , Tsong-Hua Ou , Yu-Po Tang , Wen-Chun Huang , Ru-Gun Liu , Shu-Chen Lu , Yu Lun Liu , Yao-Ching Ku , Tsai-Sheng Gau
IPC分类号： G03F1/38
CPC分类号： G06F17/5068 , G03F1/00 , G03F1/68
摘要： An intensity selective exposure photomask, also describes as a gradated photomask, is provided. The photomask includes a first region including a first array of sub-resolution features. The first region blocks a first percentage of the incident radiation. The photomask also includes a second region including a second array of sub-resolution features. The second region blocks a second percentage of the incident radiation different that the first percentage.
摘要翻译： 还提供强度选择性曝光光掩模，还描述为渐变光掩模。 光掩模包括包括第一子分解特征阵列的第一区域。 第一个区域阻止了第一个入射辐射的百分比。 光掩模还包括包括第二子分辨率特征阵列的第二区域。 第二个区域阻止了第二个百分比的入射辐射不同于第一个百分比。
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公开(公告)号：US20110217630A1
公开(公告)日：2011-09-08
申请号：US13046265
申请日：2011-03-11
申请人： George Liu , Kuei Shun Chen , Chih-Yang Yeh , Te-Chih Huang , Wen-Hao Liu , Ying-Chou Cheng , Boren Luo , Tsong-Hua Ou , Yu-Po Tang , Wen-Chun Huang , Ru-Gun Liu , Shu-Chen Lu , Yu Lun Liu , Yao-Ching Ku , Tsai-Sheng Gau
发明人： George Liu , Kuei Shun Chen , Chih-Yang Yeh , Te-Chih Huang , Wen-Hao Liu , Ying-Chou Cheng , Boren Luo , Tsong-Hua Ou , Yu-Po Tang , Wen-Chun Huang , Ru-Gun Liu , Shu-Chen Lu , Yu Lun Liu , Yao-Ching Ku , Tsai-Sheng Gau
IPC分类号： G03F1/00
CPC分类号： G06F17/5068 , G03F1/00 , G03F1/68
摘要： An intensity selective exposure photomask, also describes as a gradated photomask, is provided. The photomask includes a first region including a first array of sub-resolution features. The first region blocks a first percentage of the incident radiation. The photomask also includes a second region including a second array of sub-resolution features. The second region blocks a second percentage of the incident radiation different that the first percentage. Each of the features of the first and second array includes an opening disposed in an area of attenuating material.
摘要翻译： 还提供强度选择性曝光光掩模，还描述为渐变光掩模。 光掩模包括包括第一子分解特征阵列的第一区域。 第一个区域阻止了第一个入射辐射的百分比。 光掩模还包括包括第二子分辨率特征阵列的第二区域。 第二个区域阻止了第二个百分比的入射辐射不同于第一个百分比。 第一和第二阵列的每个特征包括设置在衰减材料区域中的开口。
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公开(公告)号：US08431291B2
公开(公告)日：2013-04-30
申请号：US13281198
申请日：2011-10-25
申请人： George Liu , Kuei Shun Chen , Chih-Yang Yeh , Te-Chih Huang , Wen-Hao Liu , Ying-Chou Cheng , Boren Luo , Tsong-Hua Ou , Yu-Po Tang , Wen-Chun Huang , Ru-Gun Liu , Shu-Chen Lu , Yu Lun Liu , Yao-Ching Ku , Tsai-Sheng Gau
发明人： George Liu , Kuei Shun Chen , Chih-Yang Yeh , Te-Chih Huang , Wen-Hao Liu , Ying-Chou Cheng , Boren Luo , Tsong-Hua Ou , Yu-Po Tang , Wen-Chun Huang , Ru-Gun Liu , Shu-Chen Lu , Yu Lun Liu , Yao-Ching Ku , Tsai-Sheng Gau
CPC分类号： G06F17/5068 , G03F1/00 , G03F1/68
摘要： An intensity selective exposure photomask, also describes as a gradated photomask, is provided. The photomask includes a first region including a first array of sub-resolution features. The first region blocks a first percentage of the incident radiation. The photomask also includes a second region including a second array of sub-resolution features. The second region blocks a second percentage of the incident radiation different that the first percentage.
摘要翻译： 还提供强度选择性曝光光掩模，还描述为渐变光掩模。 光掩模包括包括第一子分解特征阵列的第一区域。 第一个区域阻止了第一个入射辐射的百分比。 光掩模还包括包括第二子分辨率特征阵列的第二区域。 第二个区域阻止了第二个百分比的入射辐射不同于第一个百分比。
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