公开(公告)号：US20160211008A1

公开(公告)日：2016-07-21

申请号：US14913872

申请日：2013-08-28

Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP

Inventor： Melvin K. BENEDICT ,  Eric L. POPE

IPC: G11C11/406 ,  G06F3/06

CPC classification number: G11C11/406 ,  G06F3/0619 ,  G06F3/0622 ,  G06F3/0629 ,  G06F3/0673 ,  G06F11/073 ,  G06F11/0751 ,  G06F11/076 ,  G06F12/10 ,  G06F13/1636 ,  G06F21/566 ,  G11C7/02 ,  G11C11/40611 ,  G11C11/40622 ,  G11C2211/4061

Abstract: A technique includes determining that a row of memory has been activated at a threshold rate. Upon reaching the threshold rate, a refresh rate for the row of memory and an adjacent row of memory may be increased. Subsequent to the increase, the refresh rate may be returned to a default rate.

Abstract translation: 一种技术包括确定已经以阈值速率激活了一行存储器。 当达到阈值速率时，存储器行和相邻行存储器的刷新率可以增加。 在增加之后，刷新率可以返回到默认速率。

公开(公告)号：US20180218763A1

公开(公告)日：2018-08-02

申请号：US15899514

申请日：2018-02-20

Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP

Inventor： Reza M. BACCHUS ,  Melvin K. BENEDICT ,  Stephen F. CONTRERAS ,  Eric L. POPE ,  Chi K. SIDES ,  Chun-Pin HUANG

IPC: G11C11/4074 ,  G11C5/06 ,  G11C5/10

CPC classification number: G11C11/4074 ,  G11C5/04 ,  G11C5/06 ,  G11C5/10 ,  G11C5/147

Abstract: An example device in accordance with an aspect of the present disclosure includes a memory module having a voltage regulator module (VRM) to receive input power and deliver output power to components of the memory module at a first power plane. A sufficient number of stitching capacitors are to couple the first power plane to a second power plane.

公开(公告)号：US20170243626A1

公开(公告)日：2017-08-24

申请号：US15500070

申请日：2015-02-27

Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP

Inventor： Reza M. BACCHUS ,  Melvin K. BENEDICT ,  Stephen F. CONTRERAS ,  Eric L. POPE ,  Chi K. SIDES ,  Chun-Pin HUANG

IPC: G11C11/4074

CPC classification number: G11C11/4074 ,  G11C5/04 ,  G11C5/06 ,  G11C5/10 ,  G11C5/14 ,  G11C5/147 ,  G11C11/401

Abstract: An example device in accordance with an aspect of the present disclosure includes a memory module having a voltage regulator module (VRM) to receive input power and deliver output power to components of the memory module at a first power plane. At least one stitching capacitor is to couple the first power plane to a second power plane.