公开(公告)号：US20180373637A1

公开(公告)日：2018-12-27

申请号：US16062626

申请日：2015-12-21

Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP

Inventor： Joseph E FOSTER

IPC: G06F12/0888 ,  G06F12/0871 ,  G06F12/0804 ,  G06F12/0873

CPC classification number: G06F12/0888 ,  G06F12/0804 ,  G06F12/0871 ,  G06F12/0873 ,  G06F12/0877 ,  G06F2212/1021 ,  G06F2212/205

Abstract: A computing device comprises a main memory, an input-output (IO) device, and an input-output memory management unit (IOMMU). The IOMMU may receive an upstream IO write request to the main memory from the IO device, and bypass caching the write request if the write request is within a first memory region of the main memory associated with a non-volatile memory. The IOMMU may cache the write request if the write request is within a second memory region of the main memory associated with a volatile memory.

公开(公告)号：US20180267860A1

公开(公告)日：2018-09-20

申请号：US15761096

申请日：2015-09-18

Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP

Inventor： Joseph E FOSTER ,  Thierry FEVRIER ,  James Alexander FUXA

IPC: G06F11/14 ,  G06F12/06 ,  G06F12/16

CPC classification number: G06F11/1441 ,  G06F11/14 ,  G06F11/1456 ,  G06F12/0246 ,  G06F12/0646 ,  G06F12/16 ,  Y02D10/13

Abstract: A system for achieving memory persistence includes a volatile memory, a non-volatile memory, and a processor. The processor may indicate a volatile memory range for the processor to backup, and open a memory window for the processor to access. The system further includes a power supply. The power supply may provide power for the processor to backup the memory range of the volatile memory. The processor may, responsive to an occurrence of a backup event, initiate a memory transfer using the opened memory window. The memory transfer uses the processor to move the memory range of the volatile memory to a memory region of the non-volatile memory.