公开(公告)号：US09966678B2

公开(公告)日：2018-05-08

申请号：US15329474

申请日：2014-07-31

Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP

Inventor： Chin-Lung Chiang ,  Jyun-Jie Wang ,  Meng-Chen Wu ,  Raghavan V Venugopal ,  Patrick Raymond ,  Andrew Potter

IPC: H01R12/00 ,  H01R12/72 ,  H01R12/71 ,  H01R13/24

CPC classification number: H01R12/721 ,  H01R12/716 ,  H01R13/2457

Abstract: A Next Generation Form Factor (NGFF) connector apparatus can include a plurality of upper signal pins and an upper ground (GND) pin that is longer than other upper pins. The NGFF connector apparatus can also include a plurality of lower signal pins and a lower power (PWR) pin that is longer than other lower pins.

公开(公告)号：US10193251B2

公开(公告)日：2019-01-29

申请号：US15327727

申请日：2014-07-31

Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP

Inventor： Chin-Lung Chiang ,  Jyun-Jie Wang ,  Andrew Potter ,  Raghavan V Venugopal

IPC: H01R13/50 ,  H01R13/62 ,  H01R12/71 ,  H05K7/14 ,  G06F1/18 ,  H01R12/70

Abstract: A Next Generation Form Factor (NGFF) carrier includes a flat component perpendicularly connected to two flat side components to receive an NGFF module, a bar rotatably connected to the two flat side components, and a number of holds along an interior of the flat component to receive a fastener. The NGFF module is insertable in relation to the flat component when the bar is rotated to a first position and fixed on the flat component when the bar is rotated to a second position.

公开(公告)号：US10684664B2

公开(公告)日：2020-06-16

申请号：US15314785

申请日：2014-07-31

Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP

Inventor： Raghavan V. Venugopal ,  Patrick A. Raymond ,  William C. Hallowell ,  Han Wang ,  Chin-Lung Chiang ,  Jyun-Jie Wang

IPC: G06F1/26 ,  G06F11/14 ,  G06F11/20 ,  G06F11/30 ,  G06F1/30 ,  G06F3/06

Abstract: A test and diagnostics circuit, methods and systems are described. An example test and diagnostics circuit includes a controller and a power monitor coupled to the controller. A load switch on the test and diagnostics circuit selectably implements a load from among multiple load values to test a computing and/or data storage system. The test and diagnostics circuit includes circuitry connecting the controller, the power monitor and the load switch to receive a test enable signal from a non-dedicated pin in a non-volatile dual inline memory module (NV-DIMM) slot to implement a test operation on the system.