公开(公告)号：US20200242448A1

公开(公告)日：2020-07-30

申请号：US16261398

申请日：2019-01-29

Applicant: Hewlett Packard Enterprise Development LP

Inventor： JOHN PAUL STRACHAN ,  SUHAS KUMAR ,  THOMAS VAN VAERENBERGH

IPC: G06N3/04 ,  G06N3/063 ,  G06N3/08

Abstract: Staged neural networks and methods therefor are provided for solving NP hard/complete problems. In some embodiments, the methods include identifying a plurality of second NP hard/complete problems, wherein each of the second NP hard/complete problems is similar to the first NP hard/complete problem; identifying solutions to the second NP hard/complete problems; training a deep neural network with the second NP hard/complete problems and the solutions; providing the first NP hard/complete problem to the trained deep neural network, wherein the trained deep neural network generates a preliminary solution to the first NP hard/complete problem; and providing the preliminary solution to a recursive neural network configured to execute an energy minimization search, wherein the recursive neural network generates a final solution to the problem based on the preliminary solution.

公开(公告)号：US20200257653A1

公开(公告)日：2020-08-13

申请号：US16271638

申请日：2019-02-08

Applicant: Hewlett Packard Enterprise Development LP

Inventor： SUHAS KUMAR ,  RUI LIU

IPC: G06F15/80 ,  G06F9/30

Abstract: Systems and methods are provided for matrix tiling to accelerate computing in redundant matrices. The method may include identifying unique submatrices in the matrix; loading values of elements of each unique submatrix into a respective one of the array processors; applying the vector to inputs of each of the array processors; and adding outputs of the array processors according to locations of the unique submatrices in the matrix.

公开(公告)号：US20230019942A1

公开(公告)日：2023-01-19

申请号：US17378650

申请日：2021-07-16

Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP

Inventor： SUHAS KUMAR ,  JOHN PAUL STRACHAN ,  THOMAS VAN VAERENBERGH

IPC: G06N10/00 ,  G06F9/455

Abstract: Systems and methods are configured to provide a first problem to be solved to a network of memristors. A second problem to be solved can be gradually provided to the network of memristors. Controlled noise can be applied to the network of memristors for at least a portion of time during which the second problem is “gradually” provided to the network of memristors. A solution to the second problem can be determined.

公开(公告)号：US20210125667A1

公开(公告)日：2021-04-29

申请号：US16667773

申请日：2019-10-29

Applicant: Hewlett Packard Enterprise Development LP

Inventor： AMIT SHARMA ,  JOHN PAUL STRACHAN ,  SUHAS KUMAR ,  CATHERINE GRAVES ,  MARTIN FOLTIN ,  CRAIG WARNER

IPC: G11C13/00

Abstract: Systems and methods for providing write process optimization for memristors are described. Write process optimization circuitry manipulates the memristor's write operation, allowing the number of cycles in the write process is reduced. Write process optimization circuitry can include write current integration circuitry that measures an integral of a write current over time. The write optimization circuitry can also include shaping circuitry. The shaping circuitry can shape a write pulse, by determining the pulse's termination, width, and slope. The write pulse is shaped depending upon whether the target memristor device exhibits characteristics of “maladroit” cells or “adroit” cells. The pulse shaping circuitry uses the integral and measured write current to terminate the write pulse in a manner that allows the memristor, wherein having maladroit cells and adroit cells, to reach a target state. Thus, utility of memristors is enhanced by realizing an optimized write process with decrease latency and improved efficiency.